AD7884AP データシートの表示（PDF） - Analog Devices
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AD7884AP Datasheet PDF : 16 Pages
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AD7884/AD7885
TIMING CHARACTERISTICS1
(VDD = +5 V ؎ 5%, VSS = –5 V ؎ 5%, AGND = DGND = GND = 0 V. See Figures 2, 3, 4, and 5.)
Parameter
Limit at 25؇C
(All Versions)
Limit at TMIN, TMAX
(A, B, and J Versions) Unit
Conditions/Comments
t1
50
50
t2
100
100
t3
0
0
t4
60
60
t5
0
0
t62
57
57
t73
5
5
50
50
t8
40
40
t9
10
80
t10
25
25
t11
60
60
t12
60
60
t13
55
70
t14
55
70
ns min
ns max
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
CONVST Pulsewidth
CONVST to BUSY Low Delay
CS to RD Setup Time
RD Pulsewidth
CS to RD Hold Time
Data Access Time after RD
Bus Relinquish Time after RD
New Data Valid before Rising Edge of BUSY
HBEN to RD Setup Time
HBEN to RD Hold Time
HBEN Low Pulse Duration
HBEN High Pulse Duration
Propagation Delay from HBEN Falling to Data Valid
Propagation Delay from HBEN Rising to Data Valid
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2t6 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t7, quoted in the Timing Characteristics
is the true bus relinquish time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
1.6mA IOL
TO OUTPUT PIN
CL
100pF
200A IOH
2.1V
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
REV. D
–3–
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