AD7884AP データシートの表示（PDF） - Analog Devices
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AD7884AP Datasheet PDF : 16 Pages
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AD7884/AD7885
AD7884
VINV
VREF–
AD7885
VINV
VREF–
AD7885A
VINV
VREF–
± 3VINS
± 3VINF
± 3VINS
± 3VINF
± 5VINS
± 5VINF
± 3VIN
± 5VINS
± 5VINF
± 5VINS
± 5VINF
AGNDS
AGNDF
AVDD
AVSS
GND
VSS
VDD
CONVST
CS
RD
AGNDS
AGNDF
AVDD
AVSS
GND
VSS
VDD
CONVST
CS
RD
AGNDS
AGNDF
AVDD
AVSS
GND
VSS
VDD
CONVST
CS
RD
BUSY
HBEN
BUSY
HBEN
BUSY
DB0–DB15
DGND
VREF+F
VREF+S
DB0–DB7
DGND
VREF+F
VREF+S
DB0–DB7
DGND
VREF+F
VREF+S
PIN FUNCTION DESCRIPTIONS
Description
This pin is connected to the inverting terminal of an op amp, as in Figure 6, and allows
the inversion of the supplied 3 V reference.
This is the negative reference input and can be obtained by using an external amplifier to
invert the positive reference input. In this case, the amplifier output is connected to VREF–.
See Figure 6.
This is the analog input sense pin for the ± 3 V analog input range on the AD7884 and
AD7885A.
This is the analog input force pin for the ± 3 V analog input range on the AD7884 and
AD7885A. When using this input range, the ± 5VINF and ± 5VINS pins should be tied to
AGND.
This is the analog input pin for the ± 3 V analog input range on the AD7885. When using
this input range, the ± 5VINF and ± 5VINS pins should be tied to AGND.
This is the analog input sense pin for the ±5 V analog input range on the AD7884, AD7885,
and AD7885A.
This is the analog input force pin for the ±5 V analog input range on the AD7884, AD7885,
and AD7885A. When using this input range, the ± 3VINF and ± 3VINS pins should be tied
to AGND.
This is the ground return sense pin for the 9-bit ADC and the on-chip residue amplifier.
This is the ground return force pin for the 9-bit ADC and the on-chip residue amplifier.
Positive analog power rail for the sample-and-hold amplifier and the residue amplifier.
Negative analog power rail for the sample-and-hold amplifier and the residue amplifier.
This is the ground return for the sample-and-hold section.
Negative Supply for the 9-Bit ADC
Positive Supply for the 9-Bit ADC and All Device Logic
This asynchronous control input starts conversion.
Chip Select Control Input
Read Control Input. This is used in conjunction with CS to read the conversion result
from the device output latch.
High Byte Enable. Active high control input for the AD7885. It selects either the high or
the low byte of the conversion for reading.
Busy Output. The BUSY output goes low when the conversion begins and stays low until
it is completed, at which time it goes high.
16-Bit Parallel Data-Word Output on the AD7884
8-Bit Parallel Data Byte Output on the AD7885
Ground Return for All Device Logic
Reference Force Input
Reference Sense Input. The device operates from a 3 V reference.
REV. E
–7–
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