MSM9405MB データシートの表示（PDF） - Oki Electric Industry

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MSM9405MB

IrDA Communication Controller

Oki Electric Industry 

¡ Semiconductor

MSM9405

ENR bit

ENR[0]

ENR[1]

ENR[2]

ENR[3]

ENR[4]

ENR[5]

ENR[6]

ENR[7]

Table bit

This bit works as FE_IE in SIR or Extended-SIR mode, as AS_IE in MIR mode, and as ECE_IE in FIR

mode.

- FE_IE (Framing Error Interrupt Enable) (SIR mode/Extended-SIR mode): This bit enables/disables

interrupt when an FE (Framing Error : Stop bit not detected) has occurred.

- AS_IE (Abort Sequence Interrupt Enable) (MIR mode): This bit enables/disables interrupt when

an abort sequence has been received.

- ECE_IE (Encode Error Interrupt Enable) (FIR mode): This bit enables/disables interrupt when an

encode error has occurred.

OE_IE (Overrun Error Interrupt Enable) : This bit enables/disables interrupt when an OE (Overrun

error : Error that occurs when the FIFO is full upon receiving and the next character is completely

received by the RSR) has occurred.

CE_IE (CRC Error Interrupt Enable) : This bit enables/disables interrupt when a CE (CRC Error) has

occurred. This bit is valid in either Extended-SIR, MIR, or FIR mode. In SIR mode, this bit must

be set to "0" (disable).

MLE_IE (Maximum Length Error Interrupt Enable) : This bit enables/disables interrupt when an MLE

(Maximum Length Error: Error that occurs when a frame exceeding the maximum data size set by

the MDS is received) has occurred.

EOF_IE (End Of Frame Interrupt Enable) : This bit enables/disables interrupt when the last byte in

the frame's data field has been detected in either Extended-SIR, MIR, or FIR mode. In SIR mode,

this bit must be set to "0" (disable).

RXH/T_IE (Receiver High-Data-Level/Timeout Interrupt Enable) : This bit enables/disables interrupt

when the received data is at or above the receiving threshold level or time-out has occurred.

TXL_IE (Transmitter Low-Data-Level Interrupt Enable) : This bit enables/disables interrupt when the

sent data is below the sending threshold level.

TXE_IE (Transmitter Empty Interrupt Enable) : This bit enables/disables interrupt when both the

FIFO and the TSR have become empty upon sending.

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