XRT83VSH38 データシートの表示（PDF） - Exar Corporation

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XRT83VSH38

8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

Exar Corporation 

REV. 1.0.7

XRT83VSH38

8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

TABLE OF CONTENTS

GENERAL DESCRIPTION.............................................................................................................. 1

APPLICATIONS ............................................................................................................................................................... 1

FIGURE 1. BLOCK DIAGRAM OF THE XRT83VSH38 T1/E1/J1 LIU (HOST MODE) .................................................................................... 1

FIGURE 2. BLOCK DIAGRAM OF THE XRT83VSH38 T1/E1/J1 LIU (HARDWARE MODE) ........................................................................... 2

FEATURES..................................................................................................................................................................... 3

ORDERING INFORMATION .................................................................................................................... 3

TABLE OF CONTENTS ............................................................................................................ I

PIN DESCRIPTION BY FUNCTION................................................................................................ 5

RECEIVE SECTION ......................................................................................................................................................... 5

TRANSMIT SECTION ....................................................................................................................................................... 7

PARALLEL MICROPROCESSOR INTERFACE ...................................................................................................................... 9

JITTER ATTENUATOR.................................................................................................................................................... 11

CLOCK SYNTHESIZER .................................................................................................................................................. 11

ALARM FUNCTIONS/REDUNDANCY SUPPORT................................................................................................................. 13

SERIAL MICROPROCESSOR INTERFACE......................................................................................................................... 15

POWER AND GROUND.................................................................................................................................................. 15

FUNCTIONAL DESCRIPTION ...................................................................................................... 18

1.0 HARDWARE MODE VS HOST MODE ................................................................................................ 18

1.1 FEATURE DIFFERENCES IN HARDWARE MODE ...................................................................................... 18

TABLE 1: DIFFERENCES BETWEEN HARDWARE MODE AND HOST MODE................................................................................................. 18

2.0 MASTER CLOCK GENERATOR ......................................................................................................... 19

FIGURE 3. TWO INPUT CLOCK SOURCE................................................................................................................................................. 19

FIGURE 4. ONE INPUT CLOCK SOURCE ................................................................................................................................................. 19

TABLE 2: MASTER CLOCK GENERATOR ................................................................................................................................................. 19

3.0 RECEIVE PATH LINE INTERFACE .................................................................................................... 20

FIGURE 5. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH ............................................................................................................ 20

3.1 LINE TERMINATION (RTIP/RRING) .............................................................................................................. 20

3.1.1 CASE 1: INTERNAL TERMINATION.......................................................................................................................... 20

TABLE 3: SELECTING THE INTERNAL IMPEDANCE ................................................................................................................................... 20

FIGURE 6. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION .......................................................................................... 20

3.1.2 CASE 2: INTERNAL TERMINATION WITH ONE EXTERNAL FIXED RESISTOR FOR ALL MODES .................... 21

TABLE 4: SELECTING THE VALUE OF THE EXTERNAL FIXED RESISTOR.................................................................................................... 21

FIGURE 7. TYPICAL CONNECTION DIAGRAM USING ONE EXTERNAL FIXED RESISTOR ............................................................................. 21

3.2 CLOCK AND DATA RECOVERY ................................................................................................................... 22

FIGURE 8. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK..................................................................................................... 22

FIGURE 9. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK................................................................................................... 22

TABLE 5: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG ................................................................................................................ 22

3.2.1 RECEIVE SENSITIVITY .............................................................................................................................................. 22

FIGURE 10. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY ............................................................................................ 23

3.2.2 INTERFERENCE MARGIN ......................................................................................................................................... 23

FIGURE 11. TEST CONFIGURATION FOR MEASURING INTERFERENCE MARGIN......................................................................................... 23

3.2.3 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ........................................................................ 23

3.3 RECEIVE JITTER ATTENUATOR .................................................................................................................. 24

3.4 HDB3/B8ZS DECODER .................................................................................................................................. 25

3.5 RPOS/RNEG/RCLK ........................................................................................................................................ 25

FIGURE 12. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ......................................................................................... 25

FIGURE 13. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ............................................................................................ 25

3.6 RXMUTE (RECEIVER LOS WITH DATA MUTING) ....................................................................................... 26

FIGURE 14. SIMPLIFIED BLOCK DIAGRAM OF THE RXMUTE FUNCTION................................................................................................... 26

4.0 TRANSMIT PATH LINE INTERFACE ................................................................................................. 27

FIGURE 15. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH ......................................................................................................... 27

4.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 27

FIGURE 16. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK...................................................................................................... 27

FIGURE 17. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK........................................................................................................ 27

TABLE 6: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG.................................................................................................................. 28

4.2 HDB3/B8ZS ENCODER .................................................................................................................................. 28

TABLE 7: EXAMPLES OF HDB3 ENCODING ............................................................................................................................................ 28

TABLE 8: EXAMPLES OF B8ZS ENCODING............................................................................................................................................. 28

4.3 TRANSMIT JITTER ATTENUATOR ............................................................................................................... 29

I

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