XRT83VL38 データシートの表示（PDF） - Unspecified

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XRT83VL38

OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

Unspecified 

XRT83VL38

OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. 1.0.1

Transmit Pulse Shaper & Line Build Out (LBO) circuit 31

Receive Equalizer Control and Transmit Line Build-Out Settings 31

Transmit and Receive Terminations 33

RECEIVER (Channels 0 - 7) 33

Internal Receive Termination Mode 33

Receive Termination Control 33

Simplified Diagram for the Internal Receive and Transmit Termination Mode 33

Receive Terminations 34

Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0 & TXTSEL= 0) 34

Simplified Diagram for E1 in External Receive Termination Mode (RXTSEL= 0) and Internal Trans-

mit Termination Mode (TXTEL= 1) 35

TRANSMITTER (Channels 0 - 7) 35

Transmit Termination Mode 35

Termination Select Control 35

External Transmit Termination Mode 35

Transmit Terminations 36

36

36

REDUNDANCY APPLICATIONS 36

TYPICAL REDUNDANCY SCHEMES 37

Simplified Block Diagram of the Transmit Section for 1:1 & 1+1 Redundancy 38

Simplified Block Diagram - Receive Section for 1:1 and 1+1 Redundancy 38

Simplified Block Diagram - Transmit Section for N+1 Redundancy 39

Simplified Block Diagram - Receive Section for N+1 Redundancy 40

Pattern Transmit and Detect Function 41

Pattern transmission control 41

Transmit All Ones (TAOS) 41

Network Loop Code Detection and Transmission 41

Loop-Code Detection Control 41

Transmit and Detect Quasi-Random Signal Source (TDQRSS) 42

Loop-Back Modes 43

Loop-back control in Hardware mode 43

Loop-back control in Host mode 43

Local Analog Loop-Back (ALOOP) 43

Local Analog Loop-back signal flow 43

Remote Loop-Back (RLOOP) 44

Remote Loop-back mode with jitter attenuator selected in receive path 44

Remote Loop-back mode with jitter attenuator selected in Transmit path 44

Digital Loop-Back (DLOOP) 45

Digital Loop-back mode with jitter attenuator selected in Transmit path 45

Dual Loop-Back 45

Signal flow in Dual loop-back mode 45

MICROPROCESSOR INTERFACE 46

Serial Microprocessor Interface Block 46

Simplified Block Diagram of the Serial Microprocessor Interface 46

Serial Timing Information 46

Timing Diagram for the Serial Microprocessor Interface 46

II

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