XRT83VL38 データシートの表示（PDF） - Unspecified

部品番号

コンポーネント説明

一致するリスト

XRT83VL38

OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

Unspecified 

XRT83VL38

REV. 1.0.1

OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

GENERAL DESCRIPTION 1

Applications 1

Block Diagram of the XRT83VL38 T1/E1/J1 LIU (Host Mode) 1

Block Diagram of the XRT83VL38 T1/E1/J1 LIU (Hardware Mode) 2

Features 2

Ordering Information 3

Package Pin Out 4

PIN DESCRIPTION BY FUNCTION 5

Receive Sections 5

Transmitter Sections 7

Microprocessor Interface 11

jitter Attenuator 14

Clock Synthesizer 14

Alarm Functions/Redundancy Support 16

Serial Microprocessor Interface 20

Power and Ground 21

FUNCTIONAL DESCRIPTION 23

Master Clock Generator 23

Two Input Clock Source 23

One Input Clock Source 23

Master Clock Generator 24

24

RECEIVER 24

Receiver Input 24

Receive Monitor Mode 25

Receiver Loss of Signal (RLOS) 25

Simplified Diagram of -15dB T1/E1 Short Haul Mode and RLOS Condition 25

Simplified Diagram of -29dB T1/E1 Gain Mode and RLOS Condition 26

Simplified Diagram of -36dB T1/E1 Long Haul Mode and RLOS Condition 26

Simplified Diagram of Extended RLOS mode (E1 Only) 27

Receive HDB3/B8ZS Decoder 27

Recovered Clock (RCLK) Sampling Edge 27

Receive Clock and Output Data Timing 28

Jitter Attenuator 28

Gapped Clock (JA Must be Enabled in the Transmit Path) 28

Maximum Gap Width for Multiplexer/Mapper Applications 28

Arbitrary Pulse Generator for T1 and e1 29

Arbitrary Pulse Segment Assignment 29

TRANSMITTER 29

Digital Data Format 29

Transmit Clock (TCLK) Sampling Edge 29

Transmit Clock and Input Data Timing 30

Transmit HDB3/B8ZS Encoder 30

Examples of HDB3 Encoding 30

Examples of B8ZS Encoding 30

30

Driver Failure Monitor (DMO) 31

I

Share Link: