XRT83VL38 データシートの表示（PDF） - Unspecified
部品番号
コンポーネント説明
一致するリスト
XRT83VL38 Datasheet PDF : 95 Pages
| |||
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.1
FIGURE 2. BLOCK DIAGRAM OF THE XRT83VL38 T1/E1/J1 LIU (HARDWARE MODE)
MCLKE1
MCLKT1
CLKSEL[2:0]
TPOS_n/TDATA_n
TNEG_n/CODES_n
TCLK_n
RCLK_n
RNEG_n/LCV_n
RPOS_n/RDATA_n
RLOS_n
HW/HOST
GAUGE
JASEL1
JASEL0
RXTSEL
TXTSEL
TERSEL1
TERSEL0
RXRES1
RXRES0
MASTER CLOCK SYNTHESIZER
One of Eight Channels, CHANNEL_n - (n=0 : 7)
QRSS
PATTERN
GENERATOR
HDB3/
B8ZS
ENCODER
TX/RX JITTER
ATTENUATOR
TIMING
CONTROL
DFM
DRIVE
MONITOR
TX FILTER
& PULSE
SHAPER
LINE
DRIVER
QRSS ENABLE
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
REMOTE
LOOPBACK
DIGITAL
LOOPBACK
LOOPBACK
ENABLE
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
LBO[3:0]
PEAK
DETECTOR
& SLICER
NLCD ENABLE
LOS
DETECTOR
AIS
DETECTOR
EQUALIZER
CONTROL
LOCAL
ANALOG
LOOPBACK
RX
EQUALIZER
TEST
HARWARE CONTROL
MCLKOUT
TAOS_n
DMO_n
TTIP_n
TRING_n
TXON_n
RTIP_n
RRING_n
LOOP1_n
LOOP0_n
ICT
RESET
TRATIO
SR/DR
EQC[4:0]
TCLKE
RCLKE
RXMUTE
ATAOS
FEATURES
Supports Section 13 - Synchronization Interface in ITU G.703 for both Transmit and Receive Paths
Fully integrated eight channel long-haul or short-haul transceivers for E1,T1 or J1 applications
Adaptive Receive Equalizer for up to 36dB cable attenuation
Programable Transmit Pulse Shaper for E1,T1 or J1 short-haul interfaces
Five fixed transmit pulse settings for T1 short-haul applications plus a fully programmable waveform
generator for transmit output pulse shaping available for both T1 and E1 modes
Transmit Line Build-Outs (LBO) for T1 long-haul application from 0dB to -22.5dB in three 7.5dB steps
Selectable receiver sensitivity from 0 to 36dB cable loss for T1 @772kHz and 0 to 43dB for E1 @1024kHz
Receive monitor mode handles 0 to 29dB resistive attenuation along with 0 to 6dB of cable attenuation for
E1 and 0 to 3dB of cable attenuation for T1 modes
Supports 75and 120(E1), 100 (T1) and 110 (J1) applications
Internal and/or external impedance matching for 75, 100110 and 120
Tri-State transmit output and receive input capability for redundancy applications
Provides High Impedance for Tx and Rx during power off
Transmit return loss meets or exceeds ETSI 300-166 standard
On-chip digital clock recovery circuit for high input jitter tolerance
Crystal-less digital jitter attenuator with 32-bit or 64-bit FIFO selectable in transmit or receive paths
On-chip frequency multiplier generates T1 or E1 Master clocks
High receiver interference immunity
On-chip transmit short-circuit protection and limiting, and driver fail monitor output (DMO)
2
Share Link: 