AD7824 データシートの表示（PDF） - Analog Devices
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AD7824 Datasheet PDF : 16 Pages
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AD7824/AD7828
TIMING CHARACTERISTICS1
(VDD = 5 V; VREF(+) = 5 V; VREF(–) = GND = 0 V, unless otherwise noted.)
Limit at 25؇C Limit at TMIN, TMAX Limit at TMIN, TMAX
Parameter (All Grades) (K, L, B, C Grades) (T, U Grades)
Unit
Conditions/Comments
tCSS
0
0
0
tCSH
0
0
0
tAS
0
0
0
tAH
30
35
40
tRDY2
40
60
60
tCRD
2.0
2.4
2.8
tACC13
85
110
120
tACC23
50
60
70
tlNTH2
40
65
70
75
100
100
tDH4
60
70
70
tP
500
500
600
tRD
60
80
80
600
500
400
ns min
ns min
ns min
ns min
ns max
µs max
ns max
ns max
ns typ
ns max
ns max
ns min
ns min
ns max
CS to RD Setup Time
CS to RD Hold Time
Multiplexer Address Setup Time
Multiplexer Address Hold Time
CS to RDY Delay. Pull-Up
Resistor 5 kΩ.
Conversion Time, Mode 0
Data Access Time after RD
Data Access Time after INT, Mode 0
RD to INT Delay
Data Hold Time
Delay Time between Conversions
Read Pulsewidth, Mode 1
NOTES
1Sample tested at 25°C to ensure compliance. All input control signals are specified with tRISE = tFALL = 20 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2CL = 50 pF.
3Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Test Circuits
DBN
3k⍀
100pF
DGND
a. High-Z to VOH
5V
DBN
3k⍀
100pF
DGND
b. High-Z to VOL
Figure 1. Load Circuits for Data Access Time Test
DBN
3k⍀
10pF
DGND
a. VOH to High-Z
5V
DBN
3k⍀
10pF
DGND
b. VOL to High-Z
Figure 2. Load Circuits for Data Hold Time Test
REV. F
–3–
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