CS61884 データシートの表示（PDF） - Cirrus Logic

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CS61884

Octal T1/E1/J1 Line Interface Unit

Cirrus Logic 

CS61884

SYMBOL

INTL/MOT/CODEN

TXOE

CLKE

LQFP FBGA TYPE

DESCRIPTION

88

H12

Motorola/Intel/Coder Mode Select Input

Parallel Host Mode - When this pin is “Low” the micropro-

cessor interface is configured for operation with Motorola

processors. When this pin is “High” the microprocessor in-

terface is configured for operation with Intel processors.

I Hardware Mode - When the CS61884 is configured for uni-

polar operation, this pin, CODEN, configures the line

encoding/decoding function. When CODEN is low,

B8ZS/HDB3 encoders/decoders are enabled for T1/J1 or

E1 operation respectively. When CODEN is high, AMI en-

coding/decoding is activated. This is done for all eight

channels.

114 E14

Transmitter Output Enable

Host mode - Operates the same as in hardware mode. In-

I dividual drivers can be set to a high impedance state via

the Output Disable Register (12h) (See Section 14.19 on

page 39).

Hardware Mode - When TXOE pin is asserted Low, all the

TX drivers are forced into a high impedance state. All other

internal circuitry remains active.

115 E13

Clock Edge Select

In clock/data recovery mode, setting CLKE “high” will cause

RPOS/RNEG to be valid on the falling edge of RCLK and

SDO to be valid on the rising edge of SCLK. When CLKE is

I set “low”, RPOS/RNEG is valid on the rising edge of RCLK,

and SDO is valid on the falling edge of SCLK. When the

part is operated in data recovery mode, the RPOS/RNEG

output polarity is active “high” when CLKE is set “high” and

active “low” when CLKE is set “low”.

DS485F1

13

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