AX88140A データシートの表示（PDF） - Unspecified
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AX88140A Datasheet PDF : 46 Pages
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AX88140A
PRELIMINARY
4.2.8 Interrupt Enable Register (REG7)
1. The interrupt enable register (REG7) enables the interrupts reported by REG5.
2. Setting bit to 1 enables a corresponding interrupt. After a hardware or software reset, all interrupts are disabled.
Field
31:17
16
15
13
11
10
9
8
7
6
5
4
3
2
1
0
R/W/C
Description
- Reserved
R/W NI - Normal Interrupt Summary Enable
When set, normal interrupt is enabled.
When reset, no normal interrupt is enabled. This bit (REG7<16>) enables the following bits :
CSR5<0>
Transmit interrupt
CSR5<2>
Transmit buffer unavailable
CSR5<6>
Receive interrupt
CSR5<10>
Early transmit interrupt
CSR5<11>
General-purpose timer expired
R/W AI - Abnormal Interrupt Summary Enable
When set, abnormal interrupt is enabled.
When reset, no abnormal interrupt is enabled. This bit (REG7<15>) enables the following bits :
CSR5<1>
transmit process stopped
CSR5<3>
transmit jabber time-out
CSR5<5>
transmit under-flow
CSR5<7>
receive buffer unavailable
CSR5<8>
receive process stopped
CSR5<9>
receive watchdog time-out
CSR5<11>
fatal bus error
R/W FBE - Fatal Bus Error interrupt enable. Active high.
R/W GPT - General purpose Timer interrupt Enable. Active high.
R/W ETE - Early Transmit Interrupt Enable. Active high.
R/W RW - Receive Watchdog Time out interrupt Enable. Active high
R/W RS - Receive Stopped interrupt Enable. Active high.
R/W RU - Receive Buffer Unavailable interrupt Enable. Active high.
R/W RI - Receive Interrupt Enable. Active high.
R/W UN - under-flow interrupt Enable. Active high.
- Reserved.--Written as “0” for future compatibility concern.
R/W TJ - Transmit Jabber Time out interrupt Enable. Active high.
R/W TU - Transmit Buffer Unavailable interrupt Enable. Active high.
R/W TS - Transmission Stopped interrupt Enable. Active high.
R/W TI - Transmit Interrupt Enable. Active high.
Tab - 23 REG7 Interrupt Enable Register Description
4.2.9 Missed Frame and Overflow Counter (REG8)
Field
R/W
Description
31:29
28
27:17
16
15:0
-
Reserved
R/C Overflow counter overflow
Sets When the overflow counter overflows, Resets When REG8 is read.
R/C Overflow counter
Indicates the number of frames discarded because of overflow. The counter clears when read.
R/C Missed frame overflow
Sets When the missed frame counter overflows; Resets When reg8 is read.
R/C Missed Frame Counter
Indicates the number of frames discarded because no host receive descriptors were available. The counter
clears when read.
Tab - 24 REG8 Missed Frame and Overflow Counter Description
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ASIX ELECTRONICS CORPORATION
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