AX88140A データシートの表示（PDF） - Unspecified

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AX88140A

Fast Ethernet MAC Controller

Unspecified 

AX88140A

PRELIMINARY

4.2.3 Receive Poll Demand (REG2)

FIELD

31:0

R/W/C

W

DESCRIPTION

RPD - Receive Poll Demand

When written with any value, the AX88140A checks for receive descriptors to be required. If no

descriptor is available, the receive process returns to the suspended states and REG5<7> is not

asserted. If the descriptor is available the receive process resumes.

Tab - 17 REG2 Receive Poll Demand Register Description

4.2.4 Receive List Base Address (REG3)

1. The register is used to point the AX88140A to the start of receive descriptors list.

2. The descriptor list resides in physical memory space and must be longword aligned. The

AX88140A behaves UNPREDICTABLY when the list are not longword aligned.

3. Writing to REG3 is permitted only when receive process is in the stopped state. That is, the

REG3 must be written before the receive START command is given .

REG3 Receive List Base Address Register Description

FIELD

31:2

1:0

R/W/C

R/W Start of receive list

R/W Must be 00 for longword alignment

DESCRIPTION

Tab - 18 REG3 Receive List Base Address Register Description

4.2.5 Transmit List Base Address (REG4)

1. The register is used to point the AX88140A to the start of transmit descriptors list.

2. The descriptor list resides in physical memory space and must be long-word aligned. The

AX88140A behaves UNPREDICTABLY when the list are not long-word aligned.

3. Writing to REG4 is permitted only when transmit process is in the stopped state. That is, the

REG4 must be written before the transmit START command is given .

FIELD

31:2

1:0

R/W/C

R/W Start of transmit list

R/W Must be 00 for long-word alignment

DESCRIPTION

Tab - 19 REG4 Transmit List Base Address Register Description

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