FX619 データシートの表示（PDF） - CML Microsystems Plc
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FX619 Datasheet PDF : 11 Pages
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Codec Timing Information
ENCODER
CLOCK
t CH
DATA CLOCKED
ENCODER DATA
OUTPUT
t PCO
ENCODER TIMING
t CL
t IF
t CH
t IR
DECODER TIMING
DECODER
CLOCK
DATA CLOCKED
DECODER DATA
INPUT
ENCODER
OUTPUT
HIGH Z
t DR
DATA ENABLE
t SU
tH
DATA TRUE TIME
MULTIPLEXING FUNCTION
HIGH Z
t DF
TIMING
tCH Clock '1' Pulse
Width
1.0µs Min.
t Clock '0' Pulse
CL
Width
1.0µs Min.
t Clock Rise Time
IR
100ns Typ.
tIF Clock Fall Time
100ns Typ.
tSU Data Set-up Time
450ns Min.
t Data Hold Time
H
600ns Min.
t + t Data True
SU H
Time.
tPCO Clock to Output
Delay time
750ns Max.
t Data Rise Time
DR
100ns Typ.
tDF Data Fall Time
100ns Typ.
Xtal Input Frequency
1.024MHz.
Fig.4 Codec Timing Diagrams
Codec Performance ...... Using the Bit Sequence Tests (a to g) at the Decoder Input pin in accordance with
the Eurocom Specification D1 – IA8, the decoder output is as shown in Table 1.
Test Sample Rate Bit Sequence at Decoder Input
MLA
Duty cycle
Typical
Output
Level
a.
16kbit/s
32kbit/s
10110100100100101101
1011011010101001001001001001010101101101
0
- 41.5dBm0
0
- 42.0dBm0
b.
16kbit/s
32kbits
11011001001001001101
1011011010101001001000100100101011011011
0.05
- 25.0dBm0
0.05
- 25.0dBm0
c.
16kbits
10110101000100101011
0.1
- 19.0dBm0
32kbit/s
1101101101010010001000100100101011011101
0.1
- 18.5dBm0
d.
16kbit/s
11011001000010011011
0.2
- 11.0dBm0
32kbit/s
1101110110010100010000100010011010111011
0.2
- 11.5dBm0
e.
16kbit/s
11011010000010010111
0.3
- 6.5dBm0
32kbit/s
1110111011001000100000010001001101110111
0.3
- 6.5dBm0
f.
16kbit/s
11011010000001001111
0.4
- 3.0dBm0
32kbit/s
1111011101010001000000001000101011101111
0.4
- 3.0dBm0
g.
16kbit/s
11101010000000101111
0.5
32kbit/s
1111101110100010000000000100010111011111
0.5
0dBm0
0dBm0
Table 1 Bit Sequence Test Table
5
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