ADM1014 データシートの表示（PDF） - Analog Devices

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ADM1014

Dual PCI Hot-Plug™ Controller

Analog Devices 

PRELIMINARY TECHNICAL DATA

ADM1014

by the devices and their on-resistance), the thermal resistance

of the package (100oC/W), and the ambient temperature.

The maximum on-resistance of the +3.3VAUX MOSFET is

0.65⍀, that of the +12V MOSFET is 0.35⍀ and that of the –

12V MOSFET is 0.9⍀, so the power dissipation will be:

PD = (0.65 ϫ (I+3.3VAUX)2 + 0.35 ϫ (I+12V)2 + 0.9 ϫ (I-12V)2)

Where:

PD is power dissipation in Watts

I is current in Amps

Under normal operating conditions the maximum recom-

mended value for RSET is 15k⍀.

UNDERVOLTAGE SENSING

Undervoltage sensing of the +3.3V, +5V, +12V and

+3.3VAUX supplies is carried out by four voltage comparators.

The supply voltages being monitoring are applied to the

inverting inputs of these comparators, whilst reference voltages

of 2.9V, 4.6V, 10.8V and 2.9V (derived from an on-chip zener

reference) are applied to their non-inverting inputs. Should any

of the output voltages fall below the corresponding reference

voltage, the output of the comparator will go high, the fault

latch will be set, turning off all the supplies (main and auxiliary)

on that channel.

FLTN AND FAUXN OUTPUTS

The FLTN and FAUXN outputs are active-low, 3.3V compatible,

Open- Drain fault outputs. These outputs are shorted together and

then connected to the 3.3VAux supply using a 4.7k⍀ pull-up

resistors. Should an overcurrent or undervoltage event occur on one

of the supplies, main or auxiliary, then the fault latch will be set,

FLTA and FAUXA or FLTB and FAUXB will go low and all

outputs on the faulting channel will be turned off.

PROGRAMMABLE FAULT LATCH DELAY

The delay between an overcurrent or undervoltage fault occur-

ring and the outputs shutting down may be set by connecting a

capacitor between a FLTN or FAUXN output and GND. This

delays the start of the FLTN/FAUXN output 1 to 0 transition

and slows down the fall time of the FLTN/FAUXN output,

thus delaying shutdown of the outputs. If the fault latch thresh-

old (~1.6V) is reached on FLTN/FAUXN then the fault latch

will be set and the four supply outputs and the auxiliary output

will be shut down. If the fault disappears before the latching

threshold is reached, the fault latch will not be set and the

FLTN/FAUXN output will return to a high state.

This adjustable delay allows the ADM1014 to ignore overcurrent

and undervoltage transients that might otherwise cause an un-

wanted shutdown. It should be noted that if a fault is asserted

on FLTN and FAUXN at the same time, then the delay is

halved, as shown in fig. 2 and Table 1.

Figure 2. FLTN and 3V5VG Delay

TABLE 1. FLT AND 3V5VG DELAY VS. CFLT

CFLT

tA

t2A

OPEN

0.001µF

0.01µF

0.1µF

0.1µs

0.44µs

2.9µs

28µs

0.05µs

0.22µs

1.5µs

14µs

POWER CONTROL INPUTS

The PWRONA and PWRONB inputs are 3.3V CMOS-com-

patible logic inputs, which may be used to switch all four main

outputs on and off, and is also used to reset the fault latch and

turn the outputs back on after an overcurrent or undervoltage

shutdown.

When PWRON is high, the four main supplies are turned on.

With PWRON held low, the supplies are turned off. After an

overcurrent or undervoltage shutdown, PWRON should be

toggled low then high again to reset the fault latch and turn on

the outputs.

PAUXONA and PAUXONB are also 3.3V CMOS-compatible

logic inputs which perform a similar function for the +3.3V

auxiliary supplies.

POWER-ON SEQUENCE AND SOFT START

When the device is powered on with PWRON held high, the

outputs are inhibited by the power-on reset circuit and will not

become active until VCC exceeds 10V. During this time the

undervoltage comparators are inhibited and the fault latch is

held in a reset condition.

Note: the power-on reset circuit monitors 12VINA.

After the power-on delay, all five outputs are turned on simulta-

neously. The undervoltage comparators are enabled when the

voltage on the gate of the internal PMOS transistor, 12VG, has

fallen below about 400mV.

The rise time of the outputs may be controlled by connecting

capacitors between the gate and output pins of the +3.3VAUX,

+12V and -12V outputs, and from the 3V5VG pin to GND.

During output turn-on, these capacitors are charged from a

nominal 25µA current source. Limiting the output rise times

also limits the charging currents drawn by any supply

decoupling capacitors in the circuits being driven. With fast

turn-on these currents might be excessive and cause

overcurrent faults at power-on.

Care must be taken when choosing these capacitors. If the

capacitor on AUXG or 3V5VG is more than 25% larger than

REV. PrN 1/02

–9–

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