AD12400 データシートの表示（PDF） - Analog Devices
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AD12400 Datasheet PDF : 24 Pages
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AD12400
Table 4. Output Coding (Twos Complement)
Code
4095
AIN (V)
+1.6
Digital Output
0111 1111 1111
.
.
.
.
.
.
.
.
.
2048
0
0000 0000 0000
2047
−0.000781
1111 1111 1111
.
.
.
.
.
.
0
−1.6
1000 0000 0000
Table 5. Option Pin List with Necessary Associated Circuitry
Active Logic
Associated
High or Level Default Circuitry
Pin Name Low
Type Level
Within Part
RESET
Low
LVTTL High
3.74 kΩ Pull-Up
LEAD/LAG Low
LVTTL High
3.3V
ENC
ENC
100Ω
3.3V
100Ω
100Ω
PECL
DRIVER
100Ω
Figure 2. Encode Equivalent Circuit
N–1 N N+1
N+2
N+3
tEL
tEH
ENC
400MHZ
DATA OUT A
1/fS
74 CLOCK CYCLES
N – 74 N – 73
1
N
N+2
N+4
N+6
N+8
DRA
DRA
DATA OUT B
N+1
N+3
1
N+5
N+7
DRB
DRB
LEAD LAG
NOTES
1. DATA LOST DUE TO ASSERTION OF LEAD/LAG. LATENCY OF 74 ENCODE CLOCK CYCLES BEFORE DATA VALID.
2. IF A SINGLE-ENDED SINE WAVE IS USED FOR ENCODE, USE THE ZERO CROSSING POINT (AC-COUPLED) AS
THE 50% POINT AND APPLY THE SAME TIMING INFORMATION.
3. THE LEAD/LAG PIN IS USED TO SYNCHRONIZE THE COLLECTION OF DATA INTO EXTERNAL BUFFER MEMORIES.
THE LEAD/LAG PIN CAN BE APPLIED SYNCHRONOUSLY OR ASYNCHRONOUSLY TO THE AD12400. IF APPLIED
ASYNCHRONOUSLY, LEAD/LAG MUST BE HELD LOW FOR A MINIMUM OF 5ns TO ENSURE CORRECT OPERATION.
THE FUNCTION SHUTS OFF DRA AND DRB UNTIL THE LEAD/LAG PIN IS SET HIGH AGAIN. DRA AND DRB RESUME
ON THE NEXT VALID DRA AFTER LEAD/LAG IS RETURNED HIGH. IF THIS FEATURE IS NOT REQUIRED, TIE THIS
PIN TO 3.3V THROUGH A 3.74kΩ RESISTOR.
Figure 3. Timing Diagram
ENC
ENC
DATA OUT
DR
DR
tPD
tV
Figure 4. Highlighted Timing Diagram
Rev. A | Page 6 of 24
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