datasheetbank_Logo
データシート検索エンジンとフリーデータシート

AD12400 データシートの表示(PDF) - Analog Devices

部品番号
コンポーネント説明
一致するリスト
AD12400
ADI
Analog Devices ADI
AD12400 Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
AD12400
AC SPECIFICATIONS1
VA = 3.8 V, VC = 3.3 V, VD = 1.5 V, encode = 400 MSPS, 0°C ≤ TCASE ≤ 60°C, unless otherwise noted.
Table 2.
AD12400JWS
AD12400KWS
Parameter
Case Temp Test Level
Min Typ Max Min Typ Max
DYNAMIC PERFORMANCE2
SNR
Analog Input 10 MHz
Full
I
62
64.4
62
64.4
@ −1.0 dBFS 70 MHz
Full
I
61.5 64
61.5 64
128 MHz
Full
I
60
63.5
60
63.5
180 MHz
Full
I
SINAD3
60
62.5
60
62.5
Analog Input 10 MHz
Full
I
61
64
61
64
@ −1.0 dBFS 70 MHz
Full
I
60.5 64
60.5 64
128 MHz
Full
I
59
62.5
59
62.5
180 MHz
Full
I
Spurious-Free Dynamic Range3
57
61
57
61
Analog Input 10 MHz
Full
I
69
80
69
80
@ −1.0 dBFS 70 MHz
Full
I
69
84
69
84
128 MHz
Full
I
67
76
67
76
180 MHz
Full
I
Image Spur4
62
71
62
71
Analog Input 10 MHz
Full
I
60
75
62
75
@ −1.0 dBFS 70 MHz
Full
I
60
72
62
72
128 MHz
Full
I
56
70
62
70
180 MHz
Full
I
Offset Spur4
54
70
62
70
Analog Input @ −1.0 dBFS
60°C
V
65
65
Two-Tone IMD5
F1, F2 @ −6 dBFS
60°C
V
−75
−75
SWITCHING SPECIFICATIONS
Conversion Rate6
Full
IV
Encode Pulse Width High (tEH)1
60°C
V
Encode Pulse Width Low (tEL)1
60°C
V
DIGITAL OUTPUT PARAMETERS
396 400 404 396 400 404
1.25
1.25
1.25
1.25
Valid Time (tV)
Full
IV
Propagation Delay (tPD)
60°C
V
Rise Time (tR) (20% to 80%)
60°C
V
Fall Time (tF) (20% to 80%)
60°C
V
DR Propagation Delay (tEDR)
60°C
V
Data to DR Skew (tEDR − tPD)
60°C
V
Pipeline Latency7
Full
IV
1.9 2.4 3.1
1.20
1
1
3.88
2.68
74
1.9 2.4 3.1
1.20
1
1
3.88
2.68
74
Aperture Delay (tA)
60°C
IV
1.6
1.6
Aperture Uncertainty (Jitter, tJ)
60°C
V
0.4
0.4
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
MSPS
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
ns
ps rms
1 All ac specifications tested with a single-ended, 2.0 V p-p encode.
2 Dynamic performance guaranteed for analog input frequencies of 10 MHz to 180 MHz.
3 Not including image spur.
4 The image spur is at fs/2 AIN; the offset spur is at fs/2.
5 F1 = 70 MHz, F2 = 73 MHz.
6 Parts are tested with 400 MSPS encode. Device can be clocked at lower encode rates, but specifications are not guaranteed. Specifications are guaranteed by design
for encode 400 MSPS ±1%.
7 Pipeline latency is exactly 74 cycles.
Rev. A | Page 4 of 24

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]