MPC9100FA データシートの表示（PDF） - Motorola => Freescale

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MPC9100FA

Dual PLL Clock Generator

Motorola => Freescale 

MPC9100

0.01µF

0.1µF

0.1µF

0.01µF

24 23 22 21 20 19 18 17

25

16

26

15

27

14

28

13

MPC9100

29

12

30

11

31

10

32

9

12345678

0.01µF

0.1µF

0.1µF

14.318MHz

Crystal

Figure 1. Recommended External Components

(See Applications Section for Optional Analog Supply Filter)

APPLICATIONS INFORMATION

Power Supply Filtering

The MPC9100 is a mixed analog/digital product and as

such it exhibits some sensitivities that would not necessarily

be seen on a fully digital product. Analog circuitry is naturally

susceptible to random noise, especially if this noise is seen

on the power supply pins. The MPC9100 provides separate

power supplies for the output buffers (VCCO) and the internal

PLL (VCCA) of the device. The purpose of this design

technique is to try and isolate the high switching noise digital

outputs from the relatively sensitive internal analog

phase–locked loop. In a controlled environment such as an

evaluation board this level of isolation is sufficient. However,

in a digital system environment where it is more difficult to

minimize noise on the power supplies a second level of

isolation may be required. The simplest form of isolation is a

power supply filter on the VCCA pin for the MPC9100.

3.3V

RS=10–15Ω

VCCA

MPC9100

0.01µF

22µF

VCC

0.01µF

Figure 2. Power Supply Filter

MOTOROLA

4

TIMING SOLUTIONS

BR1333 — REV 5

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