XRT83SH38 データシートの表示（PDF） - Exar Corporation

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XRT83SH38

14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

Exar Corporation 

XRT83SH38

8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

PIN DESCRIPTION BY FUNCTION

RECEIVE SECTION

REV. 1.0.7

SIGNAL NAME

RXON

RLOS0

RLOS1

RLOS2

RLOS3

RLOS4

RLOS5

RLOS6

RLOS7

RCLK0

RCLK1

RCLK2

RCLK3

RCLK4

RCLK5

RCLK6

RCLK7

RNEG/LCV0

RNEG/LCV1

RNEG/LCV2

RNEG/LCV3

RNEG/LCV4

RNEG/LCV5

RNEG/LCV6

RNEG/LCV7

RPOS0

RPOS1

RPOS2

RPOS3

RPOS4

RPOS5

RPOS6

RPOS7

BGA

LEAD #

K16

C3

H4

H15

A16

V3

L2

J15

T15

B3

H3

H16

A17

U3

L3

M15

U16

A2

H2

H18

B16

T4

M4

M16

V17

B2

G2

D15

B17

U2

M3

L17

T17

TYPE

DESCRIPTION

I Receiver On

Hardware Mode Only

This pin is used to enable the receivers for all channels. By default, the receivers

are turned on in hardware mode. To turn the receivers off, this "Low".

NOTE: Internally pulled "High" with 50kΩ resistor.

O Receive Loss of Signal

When a receive loss of signal occurs according to ITU-T G.775, the RLOS pin will go

"High" for a minimum of one RCLK cycle. RLOS will remain "High" until the loss of

signal condition clears. See the Receive Loss of Signal section of this datasheet for

more details.

NOTE: This pin can be used for redundancy applications to initiate an automatic

switch to a backup card.

O Receive Clock Output

RCLK is the recovered clock from the incoming data stream. If the incoming signal

is absent or RTIP/RRING are in "High-Z", RCLK maintains its timing by using an

internal master clock as its reference. RPOS/RNEG data can be updated on either

edge of RCLK selected by RCLKE.

NOTE: RCLKE is a global setting that applies to all 8 channels.

O RNEG/LCV_OF Output

In dual rail mode, this pin is the receive negative data output. In single rail mode,

this pin is a Line Code Violation / Counter Overflow indicator. If LCV is selected by

programming the appropriate global register and if a line code violation, a bi-polar

violation, or excessive zeros occur, the LCV pin will pull "High" for a minimum of one

RCLK cycle. LCV will remain "High" until there are no more violations. However, if

OF (Overflow) is selected the LCV pin will pull "High" if the internal LCV counter is

saturated. The LCV pin will remain "High" until the LCV counter is reset.

O RPOS/RDATA Output

Receive digital output pin. In dual rail mode, this pin is the receive positive data out-

put. In single rail mode, this pin is the receive non-return to zero (NRZ) data output.

5

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