XRT83SH38 データシートの表示（PDF） - Exar Corporation

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XRT83SH38

14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

Exar Corporation 

REV. 1.0.7

XRT83SH38

8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

TABLE OF CONTENTS

GENERAL DESCRIPTION.............................................................................................................. 1

APPLICATIONS ............................................................................................................................................................... 1

FIGURE 1. BLOCK DIAGRAM OF THE XRT83SH38 T1/E1/J1 LIU (HOST MODE)....................................................................................... 1

FIGURE 2. BLOCK DIAGRAM OF THE XRT83SH38 T1/E1/J1 LIU (HARDWARE MODE) .............................................................................. 2

FEATURES..................................................................................................................................................................... 3

ORDERING INFORMATION .................................................................................................................... 3

PIN DESCRIPTION BY FUNCTION............................................................................................... 5

RECEIVE SECTION ......................................................................................................................................................... 5

TRANSMIT SECTION ....................................................................................................................................................... 8

MICROPROCESSOR INTERFACE .................................................................................................................................... 10

JITTER ATTENUATOR.................................................................................................................................................... 12

CLOCK SYNTHESIZER .................................................................................................................................................. 12

ALARM FUNCTIONS/REDUNDANCY SUPPORT................................................................................................................. 14

SERIAL PORT AND JTAG............................................................................................................................................... 16

POWER AND GROUND.................................................................................................................................................. 17

FUNCTIONAL DESCRIPTION ...................................................................................................... 19

1.0 HARDWARE MODE VS HOST MODE ................................................................................................ 19

1.1 FEATURE DIFFERENCES IN HARDWARE MODE ...................................................................................... 19

TABLE 1: DIFFERENCES BETWEEN HARDWARE MODE AND HOST MODE................................................................................................. 19

2.0 MASTER CLOCK GENERATOR ......................................................................................................... 20

FIGURE 3. TWO INPUT CLOCK SOURCE................................................................................................................................................. 20

FIGURE 4. ONE INPUT CLOCK SOURCE ................................................................................................................................................. 20

TABLE 2: MASTER CLOCK GENERATOR ................................................................................................................................................. 20

3.0 RECEIVE PATH LINE INTERFACE .................................................................................................... 21

FIGURE 5. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH ............................................................................................................ 21

3.1 LINE TERMINATION (RTIP/RRING) .............................................................................................................. 21

3.1.1 CASE 1: INTERNAL TERMINATION.......................................................................................................................... 21

TABLE 3: SELECTING THE INTERNAL IMPEDANCE ................................................................................................................................... 21

FIGURE 6. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION .......................................................................................... 22

3.1.2 CASE 2: INTERNAL TERMINATION WITH ONE EXTERNAL FIXED RESISTOR FOR ALL MODES .................... 22

TABLE 4: SELECTING THE VALUE OF THE EXTERNAL FIXED RESISTOR.................................................................................................... 22

FIGURE 7. TYPICAL CONNECTION DIAGRAM USING ONE EXTERNAL FIXED RESISTOR ............................................................................. 22

3.2 CLOCK AND DATA RECOVERY ................................................................................................................... 22

FIGURE 8. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK..................................................................................................... 23

FIGURE 9. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK................................................................................................... 23

TABLE 5: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG ................................................................................................................ 23

3.2.1 RECEIVE SENSITIVITY .............................................................................................................................................. 23

FIGURE 10. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY ............................................................................................ 24

3.2.2 INTERFERENCE MARGIN ......................................................................................................................................... 24

FIGURE 11. TEST CONFIGURATION FOR MEASURING INTERFERENCE MARGIN......................................................................................... 24

3.2.3 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ........................................................................ 24

3.2.3.1 RLOS (RECEIVER LOSS OF SIGNAL) ..................................................................................................................... 24

FIGURE 12. ANALOG RECEIVE LOS OF SIGNAL FOR T1/E1/J1................................................................................................................ 25

TABLE 6: ANALOG RLOS DECLARE/CLEAR (TYPICAL VALUES) FOR T1/E1 ............................................................................................. 25

3.2.3.2 EXLOS (EXTENDED LOSS OF SIGNAL) ................................................................................................................. 25

3.2.3.3 AIS (ALARM INDICATION SIGNAL) ......................................................................................................................... 25

3.2.3.4 FLSD (FIFO LIMIT STATUS DETECTION) ............................................................................................................... 25

3.2.3.5 LCVD (LINE CODE VIOLATION DETECTION) ........................................................................................................... 25

3.3 RECEIVE JITTER ATTENUATOR .................................................................................................................. 26

3.4 HDB3/B8ZS DECODER .................................................................................................................................. 26

3.5 RPOS/RNEG/RCLK ........................................................................................................................................ 26

FIGURE 13. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ......................................................................................... 26

FIGURE 14. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ............................................................................................ 26

3.6 RXMUTE (RECEIVER LOS WITH DATA MUTING) ....................................................................................... 27

FIGURE 15. SIMPLIFIED BLOCK DIAGRAM OF THE RXMUTE FUNCTION................................................................................................... 27

4.0 TRANSMIT PATH LINE INTERFACE ................................................................................................. 28

FIGURE 16. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH ......................................................................................................... 28

4.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 28

FIGURE 17. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK...................................................................................................... 28

FIGURE 18. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK........................................................................................................ 28

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