XRT83SH38 データシートの表示（PDF） - Exar Corporation

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XRT83SH38

14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

Exar Corporation 

XRT83SH38

8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

REV. 1.0.7

TABLE 7: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG.................................................................................................................. 29

4.2 HDB3/B8ZS ENCODER .................................................................................................................................. 29

TABLE 8: EXAMPLES OF HDB3 ENCODING ............................................................................................................................................ 29

TABLE 9: EXAMPLES OF B8ZS ENCODING............................................................................................................................................. 29

4.3 TRANSMIT JITTER ATTENUATOR ............................................................................................................... 30

TABLE 10: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS......................................................................................... 30

4.4 TAOS (TRANSMIT ALL ONES) ...................................................................................................................... 30

FIGURE 19. TAOS (TRANSMIT ALL ONES) ............................................................................................................................................ 30

4.5 TRANSMIT DIAGNOSTIC FEATURES .......................................................................................................... 30

4.5.1 ATAOS (AUTOMATIC TRANSMIT ALL ONES)......................................................................................................... 31

FIGURE 20. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION ..................................................................................................... 31

4.5.2 QRSS GENERATION.................................................................................................................................................. 31

TABLE 11: RANDOM BIT SEQUENCE POLYNOMIALS................................................................................................................................ 31

4.5.3 T1 SHORT HAUL LINE BUILD OUT (LBO) ............................................................................................................... 31

TABLE 12: SHORT HAUL LINE BUILD OUT.............................................................................................................................................. 31

4.5.4 ARBITRARY PULSE GENERATOR FOR T1 AND E1 ............................................................................................... 32

FIGURE 21. ARBITRARY PULSE SEGMENT ASSIGNMENT ......................................................................................................................... 32

4.6 DMO (DIGITAL MONITOR OUTPUT) ............................................................................................................. 32

4.7 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 33

FIGURE 22. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION ......................................................................................... 33

5.0 T1/E1 APPLICATIONS .........................................................................................................................34

5.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 34

5.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 34

FIGURE 23. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK................................................................................................ 34

5.1.2 REMOTE LOOPBACK ................................................................................................................................................ 34

FIGURE 24. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK .......................................................................................................... 34

5.1.3 DIGITAL LOOPBACK ................................................................................................................................................. 35

FIGURE 25. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK ........................................................................................................... 35

5.1.4 DUAL LOOPBACK ..................................................................................................................................................... 35

FIGURE 26. SIMPLIFIED BLOCK DIAGRAM OF DUAL LOOPBACK ............................................................................................................... 35

5.2 LINE CARD REDUNDANCY ........................................................................................................................... 36

5.2.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS .................................................................................................... 36

5.2.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY .................................................................................. 36

FIGURE 27. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR 1:1 AND 1+1 REDUNDANCY ................................................ 36

5.2.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 37

FIGURE 28. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR 1:1 AND 1+1 REDUNDANCY .................................................. 37

5.2.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 38

5.2.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 38

FIGURE 29. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR N+1 REDUNDANCY ............................................................ 38

5.2.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY ................................................................................................... 39

FIGURE 30. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR N+1 REDUNDANCY .............................................................. 39

5.3 POWER FAILURE PROTECTION .................................................................................................................. 40

5.4 OVERVOLTAGE AND OVERCURRENT PROTECTION ............................................................................... 40

5.5 NON-INTRUSIVE MONITORING .................................................................................................................... 40

FIGURE 31. SIMPLIFIED BLOCK DIAGRAM OF A NON-INTRUSIVE MONITORING APPLICATION ..................................................................... 40

6.0 MICROPROCESSOR INTERFACE ......................................................................................................41

6.1 SERIAL MICROPROCESSOR INTERFACE BLOCK .................................................................................... 41

FIGURE 32. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE ........................................................................ 41

6.1.1 SERIAL TIMING INFORMATION................................................................................................................................ 41

FIGURE 33. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE ....................................................................................... 41

6.1.2 24-BIT SERIAL DATA INPUT DESCRITPTION ......................................................................................................... 42

6.1.3 ADDR[7:0] (SCLK1 - SCLK8) ..................................................................................................................................... 42

6.1.4 R/W (SCLK9)............................................................................................................................................................... 42

6.1.5 DUMMY BITS (SCLK10 - SCLK16) ............................................................................................................................ 42

6.1.6 DATA[7:0] (SCLK17 - SCLK24) ................................................................................................................................. 42

6.1.7 8-BIT SERIAL DATA OUTPUT DESCRIPTION ......................................................................................................... 42

FIGURE 34. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE ....................................................................................... 43

TABLE 13: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 250C, VDD=3.3V± 5% AND LOAD = 10PF) ...................................... 43

6.2 PARALLEL MICROPROCESSOR INTERFACE BLOCK .............................................................................. 44

TABLE 14: SELECTING THE MICROPROCESSOR INTERFACE MODE .......................................................................................................... 44

FIGURE 35. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK ........................................................................ 44

6.3 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 45

TABLE 15: XRT83SH38 MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH INTEL AND MOTOROLA MODES45

TABLE 16: INTEL MODE: MICROPROCESSOR INTERFACE SIGNALS........................................................................................................... 45

TABLE 17: MOTOROLA MODE: MICROPROCESSOR INTERFACE SIGNALS ................................................................................................. 46

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