XRT83SH314 データシートの表示（PDF） - Exar Corporation

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XRT83SH314

14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

Exar Corporation 

XRT83SH314

14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

REV. 1.0.4

FIGURE 48. JITTER TRANSFER FUNCTION - E1 TX 1.5HZ 64BITS......................................................................................................... 54

FIGURE 49. JITTER TRANSFER FUNCTION - E1 RX 10HZ 32BITS ......................................................................................................... 55

FIGURE 50. JITTER TRANSFER FUNCTION - E1 RX 10HZ 64BITS ......................................................................................................... 56

FIGURE 51. JITTER TRANSFER FUNCTION - E1 RX 1.5HZ 64BITS ........................................................................................................ 57

4.8.2 INTRINSIC JITTER...................................................................................................................................................... 57

FIGURE 52. TEST CIRCUIT FOR INTRINSIC JITTER MEASUREMENTS ........................................................................................................ 58

FIGURE 53. INTRINSIC JITTER - T1 MAX. VALUE MEASURED .019UIPP .................................................................................................. 58

FIGURE 54. E1 INTRINSIC JITTER - MAX. VALUE MEASURED .023UIPP.................................................................................................. 59

4.8.3 JITTER TRANSFER CURVE ...................................................................................................................................... 59

FIGURE 55. TEST CIRCUIT FOR JITTER TRANSFER CURVE ..................................................................................................................... 59

5.0 MICROPROCESSOR INTERFACE BLOCK ........................................................................................60

TABLE 14: SELECTING THE MICROPROCESSOR INTERFACE MODE .......................................................................................................... 60

FIGURE 56. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK ........................................................................ 60

5.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 61

TABLE 15: XRT84SH314S MICROPROCESSOR INTERFACE SIGNALS COMMON TO BOTH INTEL AND MOTOROLA MODES .......................... 61

TABLE 16: INTEL MODE: MICROPROCESSOR INTERFACE SIGNALS........................................................................................................... 61

TABLE 17: MOTOROLA MODE: MICROPROCESSOR INTERFACE SIGNALS ................................................................................................. 62

5.2 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) ............................................................... 63

FIGURE 57. INTEL µP INTERFACE TIMING DURING PROGRAMMED I/O READ AND WRITE OPERATIONS WHEN ALE IS NOT TIED ’HIGH’ ... 64

TABLE 18: INTEL MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS .............................................................................................. 64

FIGURE 58. INTEL µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS WITH ALE HIGH......................... 65

TABLE 19: INTEL MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS .............................................................................................. 65

5.3 MPC86X MODE PROGRAMMED I/O ACCESS (SYNCHRONOUS) ............................................................. 66

FIGURE 59. MOTOROLA MPC86X µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS .......................... 67

TABLE 20: MOTOROLA MPC86X MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS ...................................................................... 67

FIGURE 60. MOTOROLA 68K µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS .................................. 68

TABLE 21: MOTOROLA 68K MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS .............................................................................. 68

6.0 REGISTER DESCRIPTIONS ................................................................................................................69

6.1 REGISTER LISTS ........................................................................................................................................... 69

TABLE 22: MICROPROCESSOR REGISTER ADDRESS (ADDR[7:0]) .......................................................................................................... 69

TABLE 23: MICROPROCESSOR REGISTER CHANNEL DESCRIPTION.......................................................................................................... 69

TABLE 24: MICROPROCESSOR REGISTER GLOBAL DESCRIPTION............................................................................................................ 70

6.2 DETAIL BIT DESCRIPTIONS ......................................................................................................................... 71

TABLE 25: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION ........................................................................................................ 71

TABLE 26: CABLE LENGTH CONTROL .................................................................................................................................................... 72

TABLE 27: MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION ........................................................................................................ 73

TABLE 28: MICROPROCESSOR REGISTER 0X02H BIT DESCRIPTION ........................................................................................................ 74

TABLE 29: MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION ........................................................................................................ 74

TABLE 30: MICROPROCESSOR REGISTER 0X04H BIT DESCRIPTION ........................................................................................................ 75

TABLE 31: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION ........................................................................................................ 76

TABLE 33: MICROPROCESSOR REGISTER 0X07H BIT DESCRIPTION ........................................................................................................ 78

TABLE 32: MICROPROCESSOR REGISTER 0X06H BIT DESCRIPTION ........................................................................................................ 78

TABLE 34: MICROPROCESSOR REGISTER 0X08H BIT DESCRIPTION ........................................................................................................ 79

TABLE 35: MICROPROCESSOR REGISTER 0X09H BIT DESCRIPTION ........................................................................................................ 79

TABLE 36: MICROPROCESSOR REGISTER 0X0AH BIT DESCRIPTION ....................................................................................................... 79

TABLE 37: MICROPROCESSOR REGISTER 0X0BH BIT DESCRIPTION ....................................................................................................... 79

TABLE 38: MICROPROCESSOR REGISTER 0X0CH BIT DESCRIPTION ....................................................................................................... 80

TABLE 39: MICROPROCESSOR REGISTER 0X0DH BIT DESCRIPTION ....................................................................................................... 80

TABLE 40: MICROPROCESSOR REGISTER 0X0EH BIT DESCRIPTION ....................................................................................................... 80

TABLE 41: MICROPROCESSOR REGISTER 0X0FH BIT DESCRIPTION........................................................................................................ 80

TABLE 42: MICROPROCESSOR REGISTER 0XE0H BIT DESCRIPTION ....................................................................................................... 81

TABLE 43: MICROPROCESSOR REGISTER 0XE1H BIT DESCRIPTION ....................................................................................................... 82

TABLE 44: MICROPROCESSOR REGISTER 0XE2H BIT DESCRIPTION ....................................................................................................... 82

TABLE 45: MICROPROCESSOR REGISTER 0XE3H BIT DESCRIPTION ....................................................................................................... 83

TABLE 46: MICROPROCESSOR REGISTER 0XE4H BIT DESCRIPTION ....................................................................................................... 83

TABLE 47: MICROPROCESSOR REGISTER 0XE5H BIT DESCRIPTION ....................................................................................................... 84

TABLE 48: MICROPROCESSOR REGISTER 0XE6H BIT DESCRIPTION ....................................................................................................... 85

TABLE 49: MICROPROCESSOR REGISTER 0XE7H BIT DESCRIPTION ....................................................................................................... 86

TABLE 50: MICROPROCESSOR REGISTER 0XE8H BIT DESCRIPTION ....................................................................................................... 86

6.2.1 CLOCK SELECT REGISTER...................................................................................................................................... 87

FIGURE 61. REGISTER 0XE9H SUB REGISTERS ..................................................................................................................................... 87

TABLE 51: MICROPROCESSOR REGISTER 0XE9H BIT DESCRIPTION ....................................................................................................... 88

TABLE 52: MICROPROCESSOR REGISTER 0XEAH BIT DESCRIPTION ....................................................................................................... 89

TABLE 53: MICROPROCESSOR REGISTER 0XEBH BIT DESCRIPTION ....................................................................................................... 89

TABLE 54: E1 ARBITRARY SELECT........................................................................................................................................................ 90

III

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