W83195BG-341 データシートの表示（PDF） - Winbond

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W83195BG-341

WINBOND CLOCK GENERATOR FOR VIA P4/KT SERIES CHIPSET

Winbond 

W83195BR-341/W83195BG-341

CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET

7.11 Register 11: Control (Default: E7h)

BIT

NAME

PWD

FUNCTION DESCRIPTION

7 CPUT_DRI 1 CPUT output state in during POWER DOWN or Stop mode assertion.

0: Driven (2*Iref), 1: Tristate (Floating)

CPUC always tri-state (floating) in power down Assertion.

6

MULTSEL

X On P4 mode CPU clock output level selection

Refer to Page 5 Table-1

Default value follow hardware trapping data on pin12 MULTSEL/PCI2

(Default 1)

5

SPCNT [5]

1 Spread Spectrum Programmable time, the resolution is 280ns.

4

SPCNT [4]

0 Default period is 11.8us

3

SPCNT [3]

0

2

SPCNT [2]

1

1

SPCNT [1]

1

0

SPCNT [0]

1

7.12 Register 12: Control (Default: 3Ch)

BIT

NAME

PWD

FUNCTION DESCRIPTION

7

INV_CPU

0 Invert the CPU phase

0: Default, 1: Inverse

6

TRI_EN

0 Tri-state all output if set 1

5 SPSP_TYPE 1 Spread spectrum implementation method

1 : Pendulum type

0 : Original

4

SPSP1

1 Spread Spectrum type select.

3

SPSP0

1

00: Down 1%

01: Down 0.5%

10: Center ± 0.5%

11: Center ± 0.25%

2

ASKEW [2]

1 CPU to AGP skew control, Skew resolution is 340ps

1

ASKEW [1]

0 Expand the skew direction is same as

0

ASKEW [0]

0 CPU_AGP_SKEW [2:0] setting

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