W83195BG-341 データシートの表示（PDF） - Winbond

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W83195BG-341

WINBOND CLOCK GENERATOR FOR VIA P4/KT SERIES CHIPSET

Winbond 

W83195BR-341/W83195BG-341

CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET

7. I2C CONTROL AND STATUS REGISTERS

(The register No. Is increased by 1 if use byte data read/write protocol)

7.1 Register 0: Frequency Select (Default =08h)

BIT

NAME

PWD

FUNCTION DESCRIPTION

7

SSEL [4]

0 Software frequency table selection through I2C

6

SSEL [3]

0

5

SSEL [2]

0

4

SSEL [1]

0

3

SSEL [0]

1

2

EN_SSEL

1

SPSPEN

0

Reserved

0 Enable software table selection FS [4:0].

0 = Hardware table setting (Jump mode).

1 = Software table setting through Bit7~3. (Jump less mode)

0 Enable spread spectrum mode under clock output.

0 = Spread Spectrum mode disable

1 = Spread Spectrum mode enable

0 Reserved

7.2 Register 1: SRC/CPU Clock (1 = Enable, 0 = Disable) (Default: A1h)

BIT

NAME

PWD

FUNCTION DESCRIPTION

7

CPUCS_T

1

Pin 48,49 CPUCS_T/C output control

CPUCS_C

6

L_MODE

0

Selection for Pin 26. Power Down

Input / System Reset Control Output

1: System Reset feature

0: Power Down feature (Default)

5

CPUT/C

1

Pin 53,52 CPUT/C output control

4

FS4

0

Mapping software table.

3

FS3

X

Power on latched value of FS3 (20)

pin. Default 0 (Read only)

2

FS2

X

Power on latched value of FS2 (21)

pin. Default 0 (Read only)

1

FS1

X

Power on latched value of FS1 (10)

pin. Default 0 (Read only)

0

FS0

X

Power on latched value of FS (1) pin.

Default 1 (Read only)

-8-

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