W83195BG-341 データシートの表示（PDF） - Winbond

部品番号

コンポーネント説明

一致するリスト

W83195BG-341

WINBOND CLOCK GENERATOR FOR VIA P4/KT SERIES CHIPSET

Winbond 

W83195BR-341/W83195BG-341

CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET

7.3 Register 2: PCI Clock (1 = Enable, 0 = Disable) (Default: FEh)

BIT

NAME

PWD

FUNCTION DESCRIPTION

7

PCI_F

1 Pin 10 PCI_F output control

6

PCI6

1 Pin 18 PCI6 output control

5

PCI5

1 Pin 17 PCI5 output control

4

PCI4

1 Pin 15 PCI4 output control

3

PCI3

1 Pin 14 PCI3 output control

2

PCI2

1 Pin 12 PCI2 output control

1

PCI1

1 Pin 11 PCI1 output control

0 INV_CPUCS 0 Invert the CPUCS phase, 0: Default, 1: Inverse

7.4 Register 3: REF, 24_48,48,AGP Clock (1 = Enable, 0 = Disable) (Default: F7h)

BIT

NAME

PWD

FUNCTION DESCRIPTION

7

PREF1

1 Pin 56 REF1 output control

6

PREF0

1 Pin 1 REF0 output control

5

PUSB24

1 Pin 21 24_48MHz output control

4

PUSB48

1 Pin 20 48MHz output control

3 INV_USB48

0 Invert the 48MHz phase, 0: In phase with 24_48MHz, 1: 180 degrees

out of phase

2

AGP2

1 Pin 8 AGP2 output control

1

AGP1

1 Pin 7 AGP1 output control

0

AGP0

1 Pin 6 AGP0 output control

7.5 Register 4,5 Reserved

7.6 Register 6: M/N Program (Default: 8Bh)

BIT

NAME PWD

FUNCTION DESCRIPTION

7 N_DIV [8] 1 Programmable N divisor value. Bit 7 ~0 are defined in the Register 7.

6 M_DIV [6] 0 Programmable M divisor value.

5 M_DIV [5] 0

4 M_DIV [4] 0

3 M_DIV [3] 1

2 M_DIV [2] 0

1 M_DIV [1] 1

0 M_DIV [0] 1

Publication Release Date: March, 2006

-9-

Revision 1.1

Share Link: