UPD72862 データシートの表示（PDF） - NEC => Renesas Technology
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UPD72862 Datasheet PDF : 36 Pages
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µPD72862
(6) W_GENERAL register (Base address + 0x950 - 0x95C)
31
0
W_GENERAL_0 (Base address + 0x950) - W_GENERAL_3 (Base address + 0x95C)
Field
Bits
W_GENERAL_0 - 31-0
W_GENERAL_3
R/W
R/W
Default value
Description
Undefined User define value. The value is loaded into GENERAL_registerA - D in
Configuration register (Offset+70H - 7BH).
(7) W_PHYS register (Base address + 0x960)
31
-0-
10 9 8 7
32
0
-0-
-1-
W_aPhyEnhanceEnable
W_programPhyEnable
Field
Bits
-
31-10
W_programPhyEnable 9
W_aPhyEnhanceEnable 8
-
7-3
2-0
R/W
-
R/W
R/W
-
-
Default value
Description
-
Reserved. Write 0 to these bits.
1
programPhyEnable bit. The bit is loaded into HCControl registers in OHCI
register ((Offset+50H bit 23) and (54H bit 23)).
Please refer to the 1394 Open Host Controller Interface Specification/Release
1.0 [5.7].
1: P1394a enhancement is supported.
0. P1394a enhancement is not supported.
0
aPhyEnhanceEnable bit. The bit is loaded into HCControl registers in OHCI
register ((Offset+50H bit 23) and (54H bit 23)).
-
Reserved. Write 0 to these bits.
-
Reserved. Write 1 to these bits.
(8) W_CIS register (Base address + 0x980 - 0x984)
31
0
W_CIS_EVEN (Base address + 0x980) - W_CIS_ODD (Base address + 0x984)
Field
W_CIS_EVEN -
W_CIS_ODD
Bits
31-0
R/W
R/W
Default value
Description
Undefined CIS Area value. The value is loaded into CIS Area in Configuration register
(Offset+80H - FCH).
Data Sheet S14265EJ2V0DS00
23
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