UPD72852 データシートの表示（PDF） - NEC => Renesas Technology

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UPD72852

IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI

NEC => Renesas Technology 

µPD72852

Field

Timeout

Port_event

Enab_accel

Enab_multi

Page_select

Port_select

Reserved

Table 2-1. Bit Field Description (3/3)

Size R/W Reset value

Description

1 R/W

0

Arbitration state machine time-out.

Writing 1 to this bit clears it to 0.

Writing 0 has no effect.

1 R/W

0

Set to 1 when the Int_enable bit in the register map of each port is 1 and

there is a change in the ports connected, Bias, Disabled and Fault bits.

Set to 1 when the Watchdog bit is 1 and any one port does resume.

Writing 1 to this bit clears it to 0.

Writing 0 has no effect.

This bit is not settable when SUS/RES(19pin) = “0”.

1 R/W

0

Enables arbitration acceleration.

Ack-acceleration and Fly-by arbitration are enabled.

1: Enabled

0: Disabled

If this bit changes while the bus request is pending, the operation is not

guaranteed.

1 R/W

0

Enable multi-speed packet concatenation.

Setting this bit to 1 follows multi-speed transmission.

When this bit is set to 0,the packet will be transmitted with the same speed

as the first packet.

3 R/W

000

Select page address between 1000 to 1111.

000: Port Status Page

001: Vendor ID Page

111: Vendor Dependent Page

Others: Unused

4 R/W

0000

Port Selection.

Selecting 000 (Port Status Page) with the Page_select selects the port.

Selecting 111 (Vendor Dependent Page) with the Page_select have to select

the Port 1.

0000: Port 0

0001: Port 1

Others: Unused

-

R

000…

Reserved. Read as 0.

Data Sheet S14920EJ3V0DS

11

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