UPD72873 データシートの表示（PDF） - NEC => Renesas Technology

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UPD72873

IEEE1394 OHCI 1.1 COMPLIANT 2PORT PHY-LINK 1-CHIP HOST CONTROLLER

NEC => Renesas Technology 

PIN NAME

µPD72873

AD0 to AD31 : PCI Multiplexed Address and Data

CARD_ON : PCI/Card Select

CBE0 to : Command/Byte Enables

CBE3

CLKRUN : PCICLK Running

CPS

: Cable Power Status Input

D3CSUP : D3cold Support

DEVSEL : Device Select

FRAME : Cycle Frame

GND

: GND

GNT

: Bus_master Grant

GROM_EN : Serial EEPROM Enable

GROM_SCL : Serial EEPROM Clock Output

GROM_SDA : Serial EEPROM Data Input / Output

IC(H)

: Internally Connected (High Clamped)

IC(L)

: Internally Connected (Low Clamped)

IC(N)

: Internally Connected (Open)

IDSEL

: ID Select

INTA

: Interrupt

IRDY

: Initiator Ready

L_VDD

: VDD for Link Digital Core and Link I/Os

PAR

: Parity

PC0 to PC2 : Power Class Input

PCI_VDD : VDD for PCI I/Os

PCLK

: PCI Clock

PERR

PME

PRST

P_AVDD

P_DVDD

P_RESET

REQ

RI0

RI1

RSMRST

SERR

STOP

TpA0n

TpA0p

TpA1n

TpA1p

TpB0n

TpB0p

TpB1n

TpB1p

TpBias0

TpBias1

TRDY

XI

XO

: Parity Error

: PME Output

: Reset

: PHY Analog VDD

: PHY Digital VDD

: PHY Power on Reset Input

: Bus_master Request

: Resistor0 for Reference Current Setting

: Resistor1 for Reference Current Setting

: Resume Reset

: System Error

: PCI Stop

: Port-1 Twisted Pair A Negative Input/Output

: Port-1 Twisted Pair A Positive Input/Output

: Port-2 Twisted Pair A Negative Input/Output

: Port-2 Twisted Pair A Positive Input/Output

: Port-1 Twisted Pair B Negative Input/Output

: Port-1 Twisted Pair B Positive Input/Output

: Port-2 Twisted Pair B Negative Input/Output

: Port-2 Twisted Pair B Positive Input/Output

: Port-1 Twisted Pair Bias Voltage Output

: Port-2 Twisted Pair Bias Voltage Output

: Target Ready

: X’tal XI

: X’tal XO

Preliminary Data Sheet S15305EJ2V0DS

5

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