UPD161623 データシートの表示（PDF） - NEC => Renesas Technology

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UPD161623

528 OUTPUT TFT-LCD SOURCE DRIVER WITH RAM

NEC => Renesas Technology 

µ PD161623

5.1.4 Chip select

The µ PD161623 has two chip select pins (/CS). The CPU parallel interface can be used only when /CS = L. When

the chip select pin is inactive, D0 to D17 are set to high impedance (invalid) and input of RS, /RD, or /WR is not active.

5.1.5 Access to display data RAM and internal registers

When the CPU accessed the µ PD161623, the CPU only has to satisfy the requirement of the cycle time (tCYC) and

can transfer data at high speeds. Usually, it is not necessary for the CPU to take wait time into consideration.

A high-speed RAM write function, as well as the ordinary RAM write function, is provided for writing data to the

display data RAM. By using the high-speed write function, data can be written to the display RAM at an access speed

two times faster than that of the ordinary RAM write function. Therefore, applications, such as motion picture display

where the display data must be rewritten at high speeds, can be supported. For details, refer to 5.2.5 High-speed

RAM write mode

Dummy data is not required when writing data. In the µ PD161623, only for reading display data, needs dummy data.

This relationship is shown in Figure 5–7.

Note that when in write mode of data at high speed for data read mode of read cycle time, this mode equals to

normal mode.

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Data Sheet S15817EJ2V0DS

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