SP8858 データシートの表示（PDF） - Zarlink Semiconductor Inc

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SP8858

1·5GHz Professional Synthesiser

Zarlink Semiconductor Inc 

SP8858

PHASE

DETECTOR GAIN

CONTROL

(SEE TABLE 3)

MSB

LSB

G2 G1 218 217 216 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 C2 C1

PHASE

DETECTOR

SENSE BIT

15-BIT PROGRAMMABLE COUNTER (M COUNTER)

4-BIT

PROGRAMMABLE

COUNTER

(A COUNTER)

CONTROL

LOGIC

(SEE

TABLE 3)

Fig. 6a F1 or F2 word, bit allocation with 416/17 selected

PHASE

DETECTOR GAIN

CONTROL

(SEE TABLE 3)

MUST BE ZERO

MSB

G2 G1 217 216 215 214 213 212 211 210 29 28 27 26 25 24 23

LSB

0 22 21 20 C2 C1

PHASE

DETECTOR

SENSE BIT

15-BIT PROGRAMMABLE COUNTER (M COUNTER)

3-BIT

CONTROL

PROGRAMMABLE LOGIC

COUNTER

(SEE

(A COUNTER) TABLE 3)

Fig. 6b F1 or F2 word, bit allocation with 48/9 selected

DUAL MODULUS

N RATIO SELECT

0 = 416/17

1 = 48/9

MSB

PD1 PD2

LSB

212 211 210 29 28 27 26 25 24 23 22 21 20 C2 C1

PHASE

DETECTOR

BISTABLE

CONTROL

(SEE TABLE 4)

13-BIT PROGRAMMABLE COUNTER (R COUNTER)

Fig. 6c Reference word bit allocation

CONTROL

LOGIC

(SEE

TABLE 3)

DATA

CLOCK

ENABLE

F1 WORD

22 BITS 0 0

22 CLOCKS

F2 WORD

22 BITS 1 0

22 CLOCKS

REF WORD

16 BITS 1 1

16 CLOCKS

DATA LOADS ON FALLING EDGES

Fig. 6d Data load sequence

Fig. 6 Data formats

7

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