SP8858 データシートの表示（PDF） - Zarlink Semiconductor Inc

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SP8858

1·5GHz Professional Synthesiser

Zarlink Semiconductor Inc 

DATA

CLOCK

2V

tS

tS1tCH

FIRST DATA BIT

tCH

tCL

LAST DATA BIT

tREP

2V

ENABLE

2V

tS-EN

tE

tREP = tCH 1 tCL MIN

tS = 50ns MIN

tCH = 100ns MIN

tCL = 100ns MIN

tE = 50ns MIN

tS-EN = [(31M)N1A]4RF INPUT (Hz)150ns

OR 14REFERENCE (Hz)150ns

WHICHEVER IS APPROPRIATE

(SEE DATA ENTRY AND CONTROL)

Fig. 4 DATA, CLOCK and ENABLE timing requirements

RF INPUT

MODULUS CONTROL

PRESCALER

4N / N11

A

COUNTER

RESET

M

COUNTER

RF INPUT 4(MN1A)

Fig. 5

SP8858

5

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