SP8858 データシートの表示（PDF） - Zarlink Semiconductor Inc
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SP8858 Datasheet PDF : 21 Pages
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SP8858
RF INPUT 10
RF INPUT 11
MODULUS CONTROL
16/17 OR 8/9
XFV
M
COUNTER
FV
A
COUNTER
fPD
RESET
15 BITS
4 BITS
PD GAIN
2 BITS
LOCK
DETECT
28 CD
27 LOCK
DETECT
F1/F2 13
F1/F2 22-BIT DATA BUFFER
DATA 14
3 BITS SELECT F1/F2
ACTIVE A
22 BITS
15
CLOCK
DATA
C1 C2 24-BIT SHIFT REGISTER
INTERFACE
LSB
MSB
16 BITS
ENABLE 16
SELECT R
POWER 6
DOWN
VREF
16-BIT REFERENCE BUFFER
SELECT MODULUS
13 BITS
XFR
R
DIVIDER
PD1
PD2
DECODE
FR
FV
XFV
PHASE CHARGE
FR DETECTOR PUMP
XFR
PD
SENSE
BUFFER
DISABLE
24 RPD
25 CP OUTPUT
25 CP REF
4 FPD*
5 FREF*
20 21
CRYSTAL
*FREF and FPD outputs are reversed by the phase detector
sense bit in the F1/F2 programming word. The pin allocations
shown are correct when the sense bit is low (see Fig. 6).
Fig. 2 SP8858 block diagram
500
400
GUARANTEED
OPERATING
300
WINDOW
48/9 MODE
200
100
50
0
0 80
GUARANTEED
OPERATING
WINDOW
416/17 MODE
TYPICAL
SENSITIVITY
500
750
1000
1500
FREQUENCY (MHz)
Fig. 3 Typical input characteristics and input drive requirements
3
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