RTL8130 データシートの表示（PDF） - Realtek Semiconductor

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RTL8130

REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH MII & AUI INTERFACE

Realtek Semiconductor 

RTL8130 Preliminary

6

R/W

RXFCE

RX Flow control Enable: The flow control is enabled in full-duplex

mode only. The default value comes from 93C46.

5-4

R

Medium

Current medium status:

Medium

Bit4

0

1

Bit5

0

NoLink UTP

1

MII

AUI

3

R

SPEED_10 Set, when current media is 10Mbps mode. Reset, when current media

is 100Mbps mode.

2

R

LINKB

Inverse of Link status. 0 = Link OK. 1 = Link Fail.

1

R

TXPF

Set, when RTL8130 sends pause packet. Reset, when RTL8130 sends

timer done packet.

0

R

RXPF

Pause Flag: Set, when RTL8130 is in backoff state because a pause

packet received. Reset, when pause state is clear.

5.13 CONFIG 3: Configuration Register3 (Offset 0059h, R/W)

Bit

R/W

Symbol

Description

7

R

GNTSel

Gnt Select: Select the Frame’s asserted time after the Grant signal has

been asserted. The Frame and Grant are the PCI signals.

0: No delay

1: delay one clock from GNT assertion.

6

R/W

PARM_En

Parameter Enable: Setting to 0 and 9346CR register EEM1=EEM0=1

enable the PHY1_PARM, PHY2_PARM, TW_PARM be written via

software.

Setting to 1 will allow parameter auto-load from 9346 and disable

writing to PHY1_PARM, PHY2_PARM and TW_PARM registers

via software. The parameter auto-loaded form 9346 is TW_PARM

only. The PHY parameters can not be auto-loaded from 9346.

5

R/W

Magic

Magic Packet: This bit is valid when the PWEn bit of CONFIG1

register is set. The RTL8130 will assert the PMEB signal to wakeup

the operating system when the magic packet is received.

Once the RTL8130 has been put into the magic packet mode, it

scans all incoming packets addressed to the node for a specific data

sequence, which indicates to the controller that this is a Magic

packet frame. A Magic packet frame must also meet the basic

requirements: Destination address + Source address + data + CRC

The destination address may be the node ID of the receiving station

or a multicast address which includes the broadcast address.

The specific sequence consists of 16 duplications of 6 byte ID

registers, with no breaks or interrupts. This sequence can be located

anywhere within the packet, but must be preceded by a

synchronization stream, 6 bytes of FFh. The device will also accept

a multicast address, as long as the 16 duplications of the IEEE

address match the address of the ID registers.

If the Node ID is 11h 22h 33h 44h 55h 66h, then the magic frame’s

format is like the following:

Destination address + source address + MISC + FF FF FF FF FF FF

+ MISC + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55

66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 +

1999/5/30

19

Ver.1.1

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