RTL8130 データシートの表示（PDF） - Realtek Semiconductor
部品番号
コンポーネント説明
一致するリスト
RTL8130 Datasheet PDF : 55 Pages
| |||
RTL8130 Preliminary
4
R/W
LWACT LWAKE active mode: The LWACT bit and LWPTN bit in CONFIG4 register
are used to program the LWAKE pin’s output signal. According to the
combination of these two bits, there may be 4 choices of LWAKE signal, i.e.,
active high, active low, positive (high) pulse, and negative (low) pulse. The
output pulse width is about 150 ms.
The default value of each of these two bits is 0, i.e., the default output signal of
LWAKE pin is an active high signal.
LWAKE output
LWACT
0
1
0
Active high*
Active low
LWPTN
1
Positive pulse
Negative pulse
* Default value.
3
R
MEMMAP Memory Mapping: The operational registers are mapped into PCI memory
space.
2
R
IOMAP
I/O Mapping: The operational registers are mapped into PCI I/O space.
1
-
-
Reserved
0
R/W
PMEn
Power Management Enable
Writable only when 93C46CR register EEM1=EEM0=1
Let A denote the New_Cap bit (bit 4 of the Status Register) in the PCI
Configuration space offset 06H.
Let B denote the Cap_Ptr register in the PCI Configuration space offset 34H.
Let C denote the Cap_ID (power management) register in the PCI
Configuration space offset 50H.
Let D denote the power management registers in the PCI Configuration space
offset from 52H to 57H.
Let E denote the Next_Ptr (power management) register in the PCI
Configuration space offset 51H.
PMEn
0
1
Description
A=B=C=E=0, D not valid
A=1, B=50h, C=01h, D valid, E=0
5.12 Media Status Register (Offset 0058h, R/W)
Bit
R/W
Symbol
Description
7
R/W
TXFCE/
Tx Flow Control Enable: The flow control is valid in full-duplex
LdTXFCE
mode only. This register’s default value comes from 93C46.
RTL8130
ANE = 1
ANE = 1
ANE = 1
ANE = 0 & full-
duplex mode
ANE = 0 & half-
duplex mode
Remote
NWAY FLY mode
NWAY mode only
No NWAY
-
-
TXFCE/LdTXFCE
R/O
R/W
R/W
R/W
invalid
NWAY FLY mode : NWAY with flow controo capability
NWAY mode only : NWAY without flow control capability
1999/5/30
18
Ver.1.1
Share Link: 