RT9644 データシートの表示（PDF） - Richtek Technology

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RT9644

ACPI Regulator/Controller for Dual Channel DDR Memory Systems

Richtek Technology 

Preliminary

RT9644/A

Pin No.

Pin Name

RT9644 RT9644A

Pin Function

A capacitor, CSS, connected between VREF_IN and ground is required. This

capacitor and the parallel combination of the Upper and Lower Divider

Impedance (RU//RL), sets the time constant for the start up ramp when

14

14 VREF_IN

transitioning from S3/S4/S5 to S0/S1/S2. The soft start capacitance will

determine the VTT_DDR soft start ramp by the above RC time constant.

CSS > (CVTT x VDDQ) / [10 x 2 x 1A x (RU//RL)]

FB is the error amplifier negative input that needs proper resistance divider

connected to VDDQ. The VDDQ synchronous DC-DC buck is simple voltage

15

15 FB

control mode. It needs a typical Type 2 compensation network from COMP to

FB (or Type 3). The reference voltage of the error amplifier is 0.8V m onitored

by under and over voltage protection.

The COMP is the output to the voltage loop error amplifier. Loop

16

16 COMP

compensation is achieved by connecting an AC network across COMP and

FB.

In RT9644, the FB4 pin connects the output of the upper V GMCH (VGMCHH)

linear regulator to this pin. The voltage at this pin is regulated via the

REFADJ4 pin (Pin 20). Generally, the FB4 is connected to VGMCHH, and

REFADJ4 = VGMCH. The VGMCHH LDO controller will set the positive input to

17

18 FB4

(VDDQ+REFADJ4)/2 as reference voltage. Then we can have the VGMCHH

equal to (VDDQ+VGMCH)/2.

In RT9644A, the FB4 is the 2nd synchronous DC-DC buck converter error

amplifier feedback. There should be the suitable AC compensation RC

network. The compensation may be Type 2 even Type 3. The feedback

voltage is monitored by the under voltage protection.

In RT9644, the FB3 pin connects the output of the lower V GMCH (VGMCH)

linear regulator to this pin through a properly sized resistor divider. The

voltage at this pin is regulated to 0.8V. This pin is monitored for under-voltage

18

20 FB3

protection.

In RT9644A, the pin connects the output of the VDAC linear regulator with

proper resister divider.

In RT9644, the DRIVE3 pin provides the gate voltage for the lower V GMCH

linear regulator pass transistor. Connect this pin to the gate terminal of an

external N-MOSFET transistor.

19

21 DRIVE3

In RT9644A, the DRIVE3 pin provides the gate voltage for the V DAC linear

regulator pass transistor. Connect this pin to the gate terminal of an external

N- MOSFET transistor.

This REFADJ4 pin controls the VGMCHH LDO controller reference voltage. To

20

--

REFADJ4 ENSURE that both upper and lower pass transistors dissipate the same

power, connecting this REFADJ4 pin to the VGMCH output rail.

The DRIVE4 pin provides the gate voltage for the upper V GMCH (VGMCHH)

21

--

DRIVE4 linear regulator. Connect this pin to the gate terminal of an external

N-MOSFET transistor.

DS9644/A-01 August 2007

To be continued

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