RT9644 データシートの表示（PDF） - Richtek Technology

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RT9644

ACPI Regulator/Controller for Dual Channel DDR Memory Systems

Richtek Technology 

RT9644/A

Preliminary

Functional Pin Description

Pin No.

RT9644

RT9644A

Pin Name

Pin Function

5VSBY is the main internal power supply. The part works at

normal operation mode (Icc_S0) and stand_by mode Icc_S5

1

1

5VSBY

(<1mA). The 5VSBY should be locally bypassed using a

0.1µF capacitor.

2

2

S3#

This pin accepts the SLP_S3# sleep state signal.

The internal LDO controller and DDR/DDR2 bus terminator

3

3

P12V

VTT_DDR regulator are powered by the P12V. P12V is

typically connected to the +12V rail of an ATX power supply.

The P12V is not necessary in S3, S4, and S5 states.

The GND terminals provide the return path for the chip.

4, 27,

4, 27,

GND

Exposed Pad (29) Exposed Pad (29)

Large ground currents flow through the Exposed pad of the

QFN package. The exposed pad must be soldered to a large

PCB and connected to GND for maximum power dissipation.

These two DDR_VTT pins (Pin 5 and 6) should be

5, 6

5, 6

DDR_VTT connected externally together. The pins are the output of

DDR/DDR2 bus terminator that active in S0 and S1 states.

These two VDDQ pins (Pin 7 and 8) should be connected

externally together to the regulated VDDQ output. The pins

7, 8

7, 8

VDDQ

are the power rail of DDT_VTT regulator. Large ground

currents flow through these VDDQ pins.

DDR_VTTSNS is used as the feedback for control of the

DDR/DDR2 bus terminator VTT_DDR regulator. Connect

9

9

DDR_VTTSNS

this pin to the DDR_VTT outputs (Pin 5 and 6) physical

desired portion.

This pin provides the gate voltage for the VTT_GMCH/CPU

10

10

DRIVE2

linear regulator. Connect this pin to the gate of an external

N-MOSFET transistor.

Connect the output of the VTT_GMCH/CPU linear regulator to

this pin through a properly sized resistor divider. The voltage

11

11

FB2

at this pin is regulated to 0.8V. This pin is also monitored for

under-voltage events.

The VIDPGD pin is an open-drain logic output that changes

to logic low if the VTT_GMCH/CPU linear regulator is out of

12

12

VIDPGD

regulation in S0/S1/S2 state. It should be externally pulled

high when VTT_GMCH/CPU is under regulated in S0, S1 and

S2 states.

VREF_OUT is a buffered version of DDR_VTT and also acts

as the reference voltage for the DDR_VTT linear regulator. It

13

13

VREF_OUT is recommended that a typical capacitance of 0.1 µF is

connected between VDDQ and VREF_OUT and also

between VREF_OUT and ground for proper operation.

Larger then 0.3µF capacitance is not recommended.

www.richtek.com

4

To be continued

DS9644/A-01 August 2007

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