RT9644 データシートの表示（PDF） - Richtek Technology

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RT9644

ACPI Regulator/Controller for Dual Channel DDR Memory Systems

Richtek Technology 

Preliminary

RT9644/A

Application Information

S5#

Overview

S3#

The RT9644/A provides complete control, drive, protection

P12V

and ACPI compliance for a regulator powering DDR memory

VDDQ

VGMCH

systems and the GMCH core and GMCH/CPU termination VTT_GMCH/CPU

rails. It is primarily designed for computer applications

VDAC

powered from an ATX power supply.

DDR_VTT

A 250kHz Synchronous Buck Regulator with a precision

0.8V reference provides the proper Core voltage to the

system memory of the computer. An internal LDO regulator

VIDPGD

t0t1 t2t3t4t5t6

TSS

>3TSS

t7 t8t9

t10 t12 t14

t15

t11 t13

with the ability to both sink and source current and an

externally available buffered reference that tracks the

Figure 2. Timing diagram for RT9644A

VDDQ output by 50% provides the VTT termination

voltage.

S5 to S0 Transition

At the onset of a mechanical start, time t0 in Figure 1,

In RT9644, a two-stage LDO controller provides the GMCH the RT9644 receives its bias voltage from the 5V Standby

core voltage. A third LDO controller is included for the bus (5VSBY). Once the 5VSBY rail has exceeded the

regulation of the GMCH/CPU termination voltage.

POR threshold, the RT9644 will remain in an internal S5

In RT9644A, a second 250kHz PWM Buck regulator,

which requires an external MOSFET driver, provides the

GMCH core voltage. This PWM regulator is 90° out of

state until both the S3# and S5# signal have transitioned

high and the 12V POR threshold has been exceeded by

the +12V rail from the ATX, which occurs at time t1.

phase with the PWM regulator used for the Memory core. Once all of these conditions are met, the PWM error

Two additional LDO controllers are included, one for the amplifier will first be reset by internally shorting the COMP

regulation of the GMCH/CPU termination rail and the pin to the FB pin. This reset lasts for 3-4 soft-start cycles,

second for the DAC.

Then digital soft-start sequence will begin. Each regulator

ACPI State Transitions

is enabled and soft-started according to a preset

sequence.

ACPI compliance is realized through the S3# and S5#

sleep signals and through monitoring of the 12V ATX bus.

Figure 1 and Figure 2 shows how the RT9644 and RT9644A

individual regulators are controlled during all state

transitions.

At time t2 the VDDQ rail and the upper VGMCH LDO rail of

RT9644 are digitally soft-started.

The digital soft-start for the PWM regulator is

accomplished by clamping the error amplifier reference

input to a level proportional to the internal digital soft-start

S5#

S3#

P12V

VDDQ

VGMCHH

VGMCH

VTT_GMCH/CPU

voltage. As the soft-start voltage slews up, the PWM

comparator generates PHASE pulses of increasing width

that charge the output capacitor(s).

This method provides a rapid and controlled rising output

voltage. The linear regulators, with the exception of the

internal DDR_VTT LDO, are soft-started in a similar manner.

DDR_VTT

VIDPGD

TSS

t0t1 t2t3t4t5t6

>3TSS

t7 t8t9

t10 t12 t14

t11 t13

Figure 1. Timing diagram for RT9644

The error amplifier reference is clamped to the internal

digital soft-start voltage. As the soft-start voltage ramps

up, the respective DRIVE pin voltages increase, thus

t15

enhancing the N-MOSFETs and charging the output

DS9644/A-01 August 2007

www.richtek.com

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