PCF8576DU/2DA/2 データシートの表示（PDF） - Philips Electronics

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PCF8576DU/2DA/2

Universal LCD driver for low multiplex rates

Philips Electronics 

Philips Semiconductors

Universal LCD driver for low

multiplex rates

Product specification

PCF8576D

6.5 Oscillator

6.5.1 INTERNAL CLOCK

The internal logic of the PCF8576D and its LCD drive

signals are timed either by its internal oscillator or by an

external clock. The internal oscillator is enabled by

connecting pin OSC to pin VSS. If the internal oscillator is

used, the output from pin CLK can be used as the clock

signal for several PCF8576Ds in the system that are

connected in cascade. After power-up, pin SDA must be

HIGH to guarantee that the clock starts.

6.5.2 EXTERNAL CLOCK

Pin CLK is enabled as an external clock input by

connecting pin OSC to VDD.

The LCD frame signal frequency is determined by the

clock frequency (fCLK).

A clock signal must always be supplied to the device;

removing the clock may freeze the LCD in a DC state.

6.6 Timing

The PCF8576D timing controls the internal data flow of the

device. This includes the transfer of display data from the

display RAM to the display segment outputs. In cascaded

applications, the correct timing relationship between each

PCF8576D in the system is maintained by the

synchronization signal at pin SYNC. The timing also

generates the LCD frame signal whose frequency is

derived from the clock frequency. The frame signal

frequency is a fixed division of the clock frequency from

either the internal or an external clock.

Frame frequency = -f-C2----L4--K--

6.7 Display register

The display latch holds the display data while the

corresponding multiplex signals are generated. There is a

one-to-one relationship between the data in the display

latch, the LCD segment outputs and each column of the

display RAM.

6.8 Segment outputs

The LCD drive section includes 40 segment outputs

S0 to S39 which should be connected directly to the LCD.

The segment output signals are generated in accordance

with the multiplexed backplane signals and with data

residing in the display latch. When less than 40 segment

outputs are required, the unused segment outputs should

be left open-circuit.

6.9 Backplane outputs

The LCD drive section includes four backplane outputs

BP0 to BP3 which should be connected directly to the

LCD. The backplane output signals are generated in

accordance with the selected LCD drive mode. If less than

four backplane outputs are required, the unused outputs

can be left open-circuit. In the 1 : 3 multiplex drive mode,

BP3 carries the same signal as BP1, therefore these two

adjacent outputs can be tied together to give enhanced

drive capabilities. In the 1 : 2 multiplex drive mode, BP0

and BP2, BP1 and BP3 respectively carry the same

signals and may also be paired to increase the drive

capabilities. In the static drive mode the same signal is

carried by all four backplane outputs and they can be

connected in parallel for very high drive requirements.

6.10 Display RAM

The display RAM is a static 40 × 4-bit RAM which stores

LCD data. A logic 1 in the RAM bit-map indicates the

on-state of the corresponding LCD segment; similarly, a

logic 0 indicates the off-state. There is a one-to-one

correspondence between the RAM addresses and the

segment outputs, and between the individual bits of a RAM

word and the backplane outputs. The first RAM column

corresponds to the 40 segments operated with respect to

backplane BP0 (see Fig.11). In multiplexed LCD

applications the segment data of the second, third and

fourth column of the display RAM are time-multiplexed

with BP1, BP2 and BP3 respectively.

When display data is transmitted to the PCF8576D, the

display bytes received are stored in the display RAM in

accordance with the selected LCD drive mode. The data is

stored as it arrives and does not wait for an acknowledge

cycle as with the commands. Depending on the current

multiplex drive mode, data is stored singularly, in pairs,

triplets or quadruplets. For example, in the 1 : 2 mode, the

RAM data is stored every second bit. To illustrate the filling

order, an example of a 7-segment numeric display

showing all drive modes is given in Fig.12; the RAM filling

organization depicted applies equally to other LCD types.

With reference to Fig.12, in the static drive mode, the eight

transmitted data bits are placed in bit 0 of eight successive

display RAM addresses. In the 1 : 2 mode, the eight

transmitted data bits are placed in bits 0 and 1 of four

successive display RAM addresses. In the 1 : 3 mode,

these bits are placed in bits 0, 1 and 2 of three successive

addresses, with bit 2 of the third address left unchanged.

This last bit may, if necessary, be controlled by an

additional transfer to this address but care should be taken

to avoid overriding adjacent data because full bytes are

always transmitted.

2004 Dec 22

16

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