PA7536 データシートの表示（PDF） - Anachip Corporation

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PA7536

PEEL Array™ Programmable Electrically Erasable Logic Array

Anachip Corporation 

Table 4. A.C Electrical Characteristics Combinatorial

Over the Operating Range

Symbol

Parameter6,12

-15/I-15

Unit

Min

Max

tPDI

Propagation delay Internal (tAL + tLC)

9

ns

tPDX

tIA

Propagation delay External (tIA + tAL +tLC + tLO)

Input or I/O pin to array input

15

ns

2

ns

tAL

Array input to LCC

tLC

LCC input to LCC output10

8

ns

1

ns

tLO

LCC output to output pin

4

ns

tOD, tOE

Output Disable, Enable from LCC output7

4

ns

tOX

Output Disable, Enable from input pin7

15

ns

This device has been designed and tested for the recommended operating conditions. Proper operation outside of these

levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage.

Figure 15. Combinatorial Timing - Waveforms and Block Diagram

7

04-02-052A

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