PA7536 データシートの表示（PDF） - Anachip Corporation
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PA7536 Datasheet PDF : 10 Pages
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Sum-A = D, T, J or Sum-A
Sum-B = Preset, K or Sum-B
Sum-C = Reset, Clock, Sum-C
Sum-D = Clock, Output Enable, Sum-D
P
D
Q
R
D Register
Q = D after clocked
Best for storage, sim ple counters,
shifters and state machines with
few hold (loop) conditions.
third, an output enable or an additional buried logic
function. The multi-function PEEL™ Array logic cells are
equivalent to two or three macrocells of other PLDs, which
have only one output per cell. They also allow registers to
be truly buried from I/O pins without limiting them to input-
only (see Figure 8 and Figure 9).
From Global Cell
Input Cell Clock
P
T
Q
R
T Register
Q toggles when T = 1
Q holds when T = 0
Best for wide binary counters (saves
product terms) and state machines
with many hold (loop) conditions.
P
J
Q
K
R
JK Register
Q toggles when J/K = 1/1
Q holds when J/K = 0/0
Q = 1 when J/K = 1/0
Q = 0 when J/K = 0/1
Combines features of both D and T
registers.
08-16-005A
Input
REG/
Latch
Q
MUX
Input Cell (INC)
Input
To
Array
From Global Cell
Input Cell Clock
Figure 5. LCC Register Types
SUM-A can serve as the D, T, or J input of the register or a
combinatorial path. SUM-B can serve as the K input, or the
preset to the register, or a combinatorial path. SUM-C can
be the clock, the reset to the register, or a combinatorial
path. SUM-D can be the clock to the register, the output
enable for the connected I/O cell, or an internal feedback
node. Note that the sums controlling clocks, resets, presets
and output enables are complete sum-of-product functions,
not just product terms as with most other PLDs. This also
means that any input or I/O pin can be used as a clock or
other control function.
Several signals from the global cell are provided primarily
for synchronous (global) register control. The global cell
signals are routed to all LCCs. These signals include a
high-speed clock of positive or negative polarity, global
preset and reset, and a special register-type control that
selectively allows dynamic switching of register type. This
last feature is especially useful for saving product terms
when implementing loadable counters and state machines
by dynamically switching from D-type registers to load and
T-type registers to count (see Figure 11).
To
Array
Input
MUX
REG/
Latch
Q
MUX
From
Logic
Control
Cell
A,B,C
or
Q
D
MUX
MUX
10
I/O Cell (IOC)
Figure 6. I/O Cell Block Diagram
D
Q
IOC/INC Register
Q = D after rising edge of clock
holds until next rising edge
L
Q
IOC/INC Latch
Q = L when clock is high
holds value when clock is low
I/O Pin
08-16-006A
Multiple Outputs Per Logic Cell
An important feature of the logic control cell is its capability
to have multiple output functions per cell, each operating
independently. As shown in Figure 4, two of the three
outputs can select the Q output from the register or the
Sum A, B or C combinatorial paths. Thus, one LCC output
can be registered, one output can be combinatorial and the
3
08-16-007A
Figure 7. IOC Register Configurations
04-02-052A
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