OM6206 データシートの表示（PDF） - Philips Electronics
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OM6206 Datasheet PDF : 36 Pages
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Philips Semiconductors
65 × 102 pixels matrix LCD driver
Product specification
OM6206
6.1.9 SDIN: SERIAL DATA LINE
Input for the data line.
6.1.10 SCLK: SERIAL CLOCK LINE
Input for the clock signal: up to 4.0 Mbits/s.
6.1.11 D/C: MODE SELECT
Input to select either command or address data input.
6.1.12 SCE: CHIP ENABLE
The enable pin allows data to be clocked in. Signal is
active LOW.
6.1.13 OSC: OSCILLATOR
When the on-chip oscillator is used this input must be
connected to VDD. An external clock signal, if used, is
connected to this input. If the oscillator and external clock
are both inhibited by connecting pin OSC to VSS, the
display is not clocked and may be left in a DC state. To
avoid this the chip should always be put into
Power-down mode before stopping the clock.
6.1.14 RES: RESET
This signal will reset the device and must be applied to
properly initialize the chip. Signal is active LOW.
7 FUNCTIONAL DESCRIPTION
7.1 Oscillator
The on-chip oscillator provides the clock signal for the
display system. No external components are required and
the OSC input must be connected to VDD. An external
clock signal, if used, is connected to this input.
7.2 Address counter
The address counter assigns addresses to the display
data RAM for writing. The X-address X6 to X0 and the
Y-address Y3 to Y0 are set separately. After a write
operation, the address counter is automatically
incremented by 1 according to bit V (see Section 7.7).
7.3 Display Data RAM (DDRAM)
The OM6206 contains a 65 × 102 bits static RAM which
stores the display data. The RAM is divided into
eight banks of 102 bytes (8 × 8 × 102 bits) and one bank
of 102 bits (1 × 102 bits). During RAM access, data is
transferred to the RAM via the serial interface. There is a
direct correspondence between X-address and column
output number.
7.4 Timing generator
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not affected by operations on the data bus.
7.5 Display address counter
The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The display status (all dots on/off and normal/inverse
video) is set by bits E and D in the command ‘Display
control’ (see Table 2).
7.6 LCD row and column drivers
The OM6206 contains 65 rows and 102 column drivers,
which connect the appropriate LCD bias voltages in
sequence to the display in accordance with the data to be
displayed. Figure 2 shows typical waveforms. Unused
outputs should be left unconnected.
2001 Nov 14
6
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