PLHS501 データシートの表示（PDF） - Philips Electronics
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PLHS501 Datasheet PDF : 12 Pages
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Philips Semiconductors Programmable Logic Devices
Programmable macro logic
PML™
Product specification
PLHS501/PLHS501I
MACRO CELL SPECIFICATIONS1 (SNAP Resource Summary Designations in Parantheses)
Commercial:Tamb = 0°C to +75°C, 4.75V ≤ VCC ≤ 5.25V, CL = 30pF, R2 = 1000Ω, R1 = 470Ω
Industrial: Tamb = –40°C to +85°C, 4.5V ≤ VCC ≤ 5.5V, CL = 30pF, R2 = 1000Ω, R1 = 470Ω
Input Buffer
(DIN501 [Non-inverting], NIN501 [Inverting])
X
I
Y
SYMBOL
∆tHL
∆tLH
MIN
0.05
–0.02
LIMITS
TYP
0.1
–0.05
MAX
0.15
–0.08
UNIT
ns/p-term
ns/p-term
PARAMETER
SYMBOL
To
(Output)
From
(Input)
MIN
tPHL
X
tPLH
X
I
4.5
I
5
tPHL
Y
tPLH
Y
I
2.5
I
4
Input Pins: 1 – 7, 9 – 14, 41 – 45, 48 – 52.
Bidirectional Pins: 15 – 18, 37 – 40.
Maximum internal fan-out: 16 p-terms on X or Y.
LIMITS
TYP
5.5
6
3
4
MAX
6.5
7.5
3.5
4.5
UNIT
ns
ns
ns
ns
NAND Output Buffer with 3-State Control
(TOU501)
NOTES
With 0 p-terms load
With 0 p-terms load
Tri–Ctrl
In
PARAMETER
SYMBOL
To
(Output)
From
(Input)
tPHL
Out
tPLH
Out
tOE2
Out
tOD2
Out
Output Pins: 24 – 27.
In
In
Tri-Ctrl
Tri-Ctrl
LIMITS
MIN
TYP
8.5
14.0
8.5
14.0
8.5
15
8.5
12.5
Internal Foldback NAND
(FBNAND)
Input
Output
Out
MAX
17.5
16
18.5
17.0
UNIT
ns
ns
ns
ns
SYMBOL
∆tPHL
∆tPLH
LIMITS
MIN
TYP MAX
0.05
0.1
0.15
–0.0 –0.05 –0.1
PARAMETER
LIMITS
SYMBOL
To
(Output)
From
(Input)
MIN
TYP MAX
tPHL
tPLH
Out
Any
4.0
4.5
6.8
5.5
6.5
8
Maximum internal loading of 16 terms.
Notes are on following page.
UNIT
ns/p-term
ns/p-term
UNIT
ns
ns
NOTES
With 0 p-terms load
October 22, 1993
9
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