PLHS501 データシートの表示（PDF） - Philips Electronics
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PLHS501 Datasheet PDF : 12 Pages
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Philips Semiconductors Programmable Logic Devices
Programmable macro logic
PML™
Product specification
PLHS501/PLHS501I
FEATURES
• Programmable Macro Logic device
• Full connectivity
• TTL compatible
• SNAP development system:
– Supports third-party schematic entry
formats
– Macro library
– Versatile netlist format for design
portability
– Logic, timing, and fault simulation
• Delay per internal NAND function = 6.5ns
(typ)
• Testable in unprogrammed state
• Security fuse allows protection of
proprietary designs
STRUCTURE
• NAND gate based architecture
– 72 foldback NAND terms
• 136 input-wide logic terms
• 44 additional logic terms
• 24 dedicated inputs (I0 – I23)
• 8 bidirectional I/Os with individual 3-State
enable:
– 4 Active-High (B4 – B7)
– 4 Active-Low (B0 – B3)
• 16 dedicated outputs:
– 4 Active-High outputs
O0, O1 with common 3-State enable
O2, O3 with common 3-State enable
– 4 Active-Low outputs:
O4, O5 with common 3-State enable
O6, O7 with common 3-State enable
– 8 Exclusive-OR outputs:
X0, X1 with common 3-State enable
X2, X3 with common 3-State enable
X4, X5 with common 3-State enable
X6, X7 with common 3-State enable
PIN CONFIGURATION
A Package
(52-pin PLCC)
I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5
7 6 5 4 3 2 1 52 51 50 49 48 47
VCC 8
I18 9
I19 10
I20 11
I21 12
I22 13
I23 14
B4 15
B5 16
B6 17
B7 18
O0 19
GND 20
46 VCC
45 I4
44 I3
43 I2
42 I1
41 I0
40 B3
39 B2
38 B1
37 B0
36 X7
35 X6
34 GND
21 22 23 24 25 26 27 28 29 30 31 32 33
O1 O2 O3 O4 O5 O6 O7 X0 X1 X2 X3 X4 X5
DESCRIPTION
The PLHS501 is a high-density Bipolar
Programmable Macro Logic device. PML
incorporates a programmable NAND
structure. The NAND architecture is an
efficient method for implementing any logic
function. The SNAP software development
system provides a user friendly environment
for design entry. SNAP eliminates the need
for a detailed understanding of the PLHS501
architecture and makes it transparent to the
user. PLHS501 is also supported on the
Philips Semiconductors SNAP software
development systems.
The PLHS501 is ideal for a wide range of
microprocessor support functions, including
bus interface and control applications.
The PLHS501 is also processed to industrial
requirements for operation over an extended
temperature range of –40°C to +85°C and
supply voltage of 4.5V to 5.5V.
ARCHITECTURE
The core of the PLHS501 is a programmable
fuse array of 72 NAND gates. The output of
each gate folds back upon itself and all other
NAND gates. In this manner, full connectivity
of all logic functions is achieved in the
PLHS501. Any logic function can be created
within the core of the device without wasting
valuable I/O pins. Furthermore, a speed
advantage is acquired by implementing
multi-level logic within a fast internal core
without incurring any delays from the I/O
buffers.
PML is a trademark of Philips Semiconductors
October 22, 1993
1
853–1207 11164
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