PLHS501 データシートの表示（PDF） - Philips Electronics

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PLHS501

Programmable macro logic PML™

Philips Electronics 

Philips Semiconductors Programmable Logic Devices

Programmable macro logic

PML™

Product specification

PLHS501/PLHS501I

PLHS501 GATE AND SPEED ESTIMATE TABLE

FUNCTION

INTERNAL NAND

EQUVALENT

TYPICAL tPD

Gates

NANDs

ANDs

NORs

ORs

1

6.5ns

1

6.5ns

1

6.5ns

1

6.5ns

Decoders

3-to-8

4-to-16

5-to-32

8

11ns

16

11ns

32

11ns

Encoders

8-to-3

16-to-4

32-to-5

15

11ns

32

11ns

41

11ns

Multiplexers

4-to-1

8-to-1

16-to-1

27-to-1

5

11ns

9

11ns

17

11ns

28

11ns

Flip-Flops

D-type Flip-Flop

6

T-type Flip-Flop

6

J-K-type Flip-Flop

10

Adders

8-bit

45

15.5ns

Barrel Shifters

8-bit

72

11ns

Latches

D-latch

3

fMAX

30MHz

30MHz

30MHz

COMMENTS

For 1 to 32 input variables

For 1 to 32 input variables

For 1 to 32 input variables

For 1 to 32 input variables

Inverted inputs available

Inverted inputs available

Inverted inputs available (24 chip outputs only)

Inverted inputs, 2 logic levels

Inverted inputs, 2 logic levels

Inverted inputs, 2 logic levels, factored solution.

Inverted inputs available

Can address only 27 external inputs - more if internal

With asynchronous S-R

With asynchronous S-R

With asynchronous S-R

Full carry-lookahead (four levels of logic)

2 levels of logic

2 levels of logic with one shared gate

October 22, 1993

11

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