NJU3505L データシートの表示（PDF） - Japan Radio Corporation

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NJU3505L

4-BIT SINGLE CHIP MICRO CONTROLLER

Japan Radio Corporation  

NJU3505

s INPUT OUTPUT PORT

The NJU3505 prepares 21 Input-Output lines and 14 dual-function lines for the interface to an external

application circuit. All lines are assigned to each Peripheral Register.

Data reading operation from the peripheral register can input the actual signals through the input terminal.

Data writing operation to the peripheral register can output the actual signals through the output terminal.

[ PORT FUNCTION TABLE ]

PORT NAME

FUNCTION

PORTA Input / Output port or AIN4 − AIN7

PORTB

PORTC −

PORTH

PORTI

Input / Output port

Input / Output port

Input port or AIN0 − AIN3

INPUT/OUTPUT

Programmable Input / Output PORT(4-bit).

Programmable Input / Output PORT(4-bit).

Input / Output selectable ports by the mask option.

Input

PORTJ(PJ0) Input port or VREF

PORTJ(PJ1) Input port or ADCK

Input

Input

PORTK(PK0) Input port or EXTI

Input

PORTK(PK1) Input port or CNTI

Input

PORTL(PL0) Output Port or SDO

output

PORTL(PL1) Input / Output port or SDI(O)

Input / Output selectable ports by the mask option.

Note1) PORTG is not prepared on the NJU3505L(SDIP package).

Note2) Pull-up resistance is selected by the mask option.(refer !INPUT OUTPUT TERMINAL TYPE)

(1) INPUT OUTPUT PORT

• PORTA(PA0 − PA3)

PORTA is a 4-bit programmable input-output PORT. It operates also as the multiplexed 4-channel

analog signal input terminals (AIN4 to AIN7) to the internal A/D converter by the mask option. It is set as

the output when LSB of the programmable input/output control register (PHY29) is set to “1”, and is set as

the input when LSB of PHY29 is set to “0”. When the PORT is set as the output, the 4-bit signals are

output through the output terminals by writing data into the peripheral register assigned for PORTA

(PHY17). PHY17 as the output register should be written the output data before the PORTA is set as the

output by PHY29, because the conditions of the output terminals are unknown while the output data is not

written in PHY17. When this PORT is set as the input, the 4-bit external signals are gotten directly

through the input terminals by reading data from PHY17. PHY17 can be written or read independent of

the state of PHY29 as the input or output.

PORTA is set as the input in accordance with the state of PHY29 set to “0” on the “RESET” operation.

Though the output circuit is Nch open drain type, the C-MOS input buffer is connected to the same

terminal. Therefore, the operating current of the chip by the short circuit current when the middle level

voltage between VDD and VSS is input to this terminal.

[ READING PORTA INPUT DATA (PHY17) ]

(MSB) 3

2

1

0 (LSB)

PHY17 PA3 PA2 PA1 PA0

PORTA Input Data

[ WRITING PORTA OUTPUT DATA (PHY17) ]

(MSB) 3

2

1

0 (LSB)

PHY17 PA3 PA2 PA1 PA0

PORTA Output Data

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