NJU3502L データシートの表示（PDF） - Japan Radio Corporation

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NJU3502L

4-BIT SINGLE CHIP MICRO CONTROLLER

Japan Radio Corporation  

NJU3502

• PROGRAM COUNTER(PC)

PROGRAM COUNTER(PC) consisted of the 10-bit binary counter stores the address for the next

operating instruction in ROM. Data figures limited from b0 to b5 on the PC indicate the address in a page,

and data figures limited from b6 to b9 on the PC indicate the page in ROM. Although the ROM address

can be indicated 1024 addresses continuously, the target address of JMP instruction is restricted by

Paging structure in ROM.

The PC condition is set to “0” on the “RESET” operation.

(MSB) 9

8

7

6

5

4

3

2

1

0 (LSB)

Page allocation

Address location

JMP instruction can branch to the optional address in the page. The target address is indicated by the

data figures limited from b0 to b5(6 bits) on PC as shown in above. The paging structure can reduce the

program size in ROM and the JMP instruction execution time against JPL instruction because JMP

instruction is consisted of one byte(8 bits) length. JPL and CALL instructions can branch to the optional

address without considering the paging structure, because they consists of two bytes(16 bits) length

including the 10 bits of PC.

• STACK

STACK consists of three types of registers which are the 8 by 10 bits, the 5 by 4 bits, and the 2 by 1 bit

registers. The registers of STACK hold the data of PC automatically when the interrupt routine or the

subroutine is called. The 5 by 4 bits registers of STACK hold the data of the internal registers

automatically when the interrupt operation is executed. The 2 by 1 bit registers of STACK hold the data of

the internal flag automatically when the interrupt operation is executed. In the return (RET or RETI)

operation, PC, the internal registers, and the internal flags registers get the held data from STACK

automatically.

[For branch(CALL) and interrupt operation]

STACK POINTER 9

0

000

PC

001

PC

010

PC

011

PC

100

PC

101

PC

110

PC

111

PC

[For interrupt operation]

3

0

0

AC

X-register

RPC

X'-register

Y-register

Y'-register

0

STATUS

• STACK POINTER(SP)

STACK POINTER(SP) consists of the 3 bits binary counter. SP indicates the number of next operating

position in the STACK. It counts one up(increment) after the subroutine call(CALL) or the interrupt

operation, and it counts one down(decrement) after the return(RET or RETI) operation.

Data storing operation to STACK after that SP overflowed(over than 7) or under flowed(under than 0),

breaks the former held data in STACK. Therefore the subroutine nesting level must be cautioned in the

application program.

SP condition is set to "0" on “RESET” operation.

-7-

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