MX7824KCAG データシートの表示（PDF） - Maxim Integrated
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MX7824KCAG Datasheet PDF : 12 Pages
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CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
_____________________________________________________________Pin Descriptions
PIN
MAX154
MX7824
NAME
1
AIN4
2
AIN3
3
AIN2
4
AIN1
5
REF OUT
TP
6
DBO
7
DB1
8
DB2
9
DB3
10
–R—D–
11
INT
12
GND
13
VREF-
14
VREF+
15
RDY
16
–C—S–
17
DB4
18
DB5
19
DB6
20
DB7
21
A1
22
A0
23
NC
24
VDD
FUNCTION
Analog Input Channel 4
Analog Input Channel 3
Analog Input Channel 2
Analog Input Channel 1
Reference Output (2.5V) for MAX154.
Test point for MX7824. Do not connect.
Three-State Data Output, bit 0 (LSB)
Three-State Data Output, bit 1
Three-State Data Output, bit 2
Three-State Data Output, bit 3
Read Input. –R—D– controls conversions
and data access. See Digital Interface
section.
Interrupt Output. INT going low indi-
cates the completion of a conversion.
See Digital Interface section.
Ground
Lower Limit of Reference Span. Sets
the zero-code voltage.
Range: GND to VREF+.
Upper Limit of Reference Span. Sets
the full-scale input voltage.
Range: VREF- to VDD.
Ready Output. Open-drain output with
nwoheanct–Ci—vS–e
pull-up device. Goes low
goes low and high imped-
ance at the end of a conversion.
Chip-Select Input. –C—S– must be low for
the device to be selected.
Three-State Data Output, bit 4
Three-State Data Output, bit 5
Three-State Data Output, bit 6
Three-State Data Output, bit 7 (MSB)
Channel Address 1 Input
Channel Address 0 Input
No Connect
Power-Supply Voltage, +5V
PIN
MAX158
MX7828
1
2
3
4
5
6
7
8
9
10
11
NAME
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
REF OUT
TP
DB0
DB1
DB2
DB3
12
–R—D–
13
INT
14
GND
15
VREF-
16
VREF+
17
RDY
18
C–—S–
19
DB4
20
DB5
21
DB6
22
DB7
23
A2
24
A1
25
A0
26
VDD
27
AIN8
28
AIN7
FUNCTION
Analog Input Channel 6
Analog Input Channel 5
Analog Input Channel 4
Analog Input Channel 3
Analog Input Channel 2
Analog Input Channel 1
Reference Output (2.5V) for MAX158.
Test point for MX7828. Do not connect.
Three-State Data Output, bit 0 (LSB)
Three-State Data Output, bit 1
Three-State Data Output, bit 2
Three-State Data Output, bit 3
Read Input. –R—D– controls conversions
and data access. See Digital Interface
section.
Interrupt Output. INT going low indi-
cates the completion of a conversion.
See Digital Interface section.
Ground
Lower Limit of Reference Span. Sets
the zero-code voltage.
Range: GND to VREF+.
Upper Limit of Reference Span. Sets
the full-scale input voltage.
Range: VREF- to VDD.
Ready Output. Open-drain output with
nwoheanct–Ci—vS–e
pull-up device. Goes low
goes low and high imped-
ance at the end of a conversion.
Chip-Select Input. –C—S– must be low for
the device to be selected.
Three-State Data Output, bit 4
Three-State Data Output, bit 5
Three-State Data Output, bit 6
Three-State Data Output, bit 7 (MSB)
Channel Address 2 Input
Channel Address 1 Input
Channel Address 0 Input
Power-Supply Voltage, +5V
Analog Input Channel 8
Analog Input Channel 7
_______________________________________________________________________________________ 5
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