MSM7731-02 データシートの表示（PDF） - Oki Electric Industry

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MSM7731-02

Dual Echo Canceler & Noise Canceler with Dual Codec for Hands-Free

Oki Electric Industry 

1Semiconductor

FEDL7731-02-04

MSM7731-02

AGND

This is analog ground pin.

DGND1, DGND2

These are the digital ground pins.

AVDD

This is the analog +3 V power supply pin.

DVDD1, DVDD2

These are the digital +3 V power supply pins.

SG

This is the output pin for the analog signal ground potential. The output voltage is approximately 1.4 V.

Insert 10 µF and 0.1 µF ceramic bypass capacitors between the AGND and SG pin. At power-down rest, this

output becomes 0 V.

PDN/RST

This is the power-down reset control input pin. If a logic “0” is input to this pin, the device enters the power-down

state. At this time, all control register bits, internal variables, and coefficients of echo cancelers and noise cancelers

will be reset. After the power-down reset state is released, the device enters the initial mode (refer to the CR0

control register description). During normal operation, set this pin to a logic “1”. The PDN/RST pin is ORed

(negative logic) with CR0-B7 of the control register. Refer to the section “RELATIONSHIP BETWEEN PINS

AND CONTROL REGISTERS”.

MCK/X1

This is the master clock input pin. The clock frequency is 19.2 MHz. The input clock may be asynchronous with

respect to the SYNC signal or the BCLK signal. Refer to Figure 2 (a) for an example application of an external

clock and Figure 2 (b) for an example oscillator circuit.

X2

This is the crystal oscillator output pin. If an existing external clock is to be used, leave this pin open and input the

clock to the MCK pin. Refer to Figure 2 (b) for an example oscillator circuit.

MCK/X1

X2

MCK/X1

R

X’tal

C

X2

C

X’tal (19.2 MHz)

HC-49/U

CX-91F

C

10 pF

T.B.D

R

1 MΩ

T.B.D

Figure 2 (a) External Clock

Figure2 (b) Oscillator Circuit

Application Example

Example

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