MSM7731-02 データシートの表示（PDF） - Oki Electric Industry
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MSM7731-02 Datasheet PDF : 53 Pages
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1Semiconductor
FEDL7731-02-04
MSM7731-02
Digital Interface Characteristics (2/3)
Parameter
Bit Clock Frequency
Bit Clock Duty Ratio
Sync signal frequency
Sync signal Duty Ratio
Transmit/Receive Sync
Signal Setting Time
Input Setup Time
Input Hold Time
Digital Output Delay Time
Digital Output Hold Time
Symbol
fBCK
DCK
fSYNC
DSYNC
tBS
tSB
tDS
tDH
tSDX
tXD1
tXD2
tXD3
Condition
CDL = 20 pF
(output mode, PCM)
CDL = 20 pF
(output mode, linear)
CDL = 20 pF (output mode)
CDL = 20 pF (output mode)
CDL = 20 pF (output mode)
BCLK to SYNC
(output mode)
SYNC to BCLK
(output mode)
—
—
RDL = 1 kΩ, CDL = 50 pF
RDL = 1 kΩ, CDL = 50 pF
RDL = 1 kΩ, CDL = 50 pF
RDL = 1 kΩ, CDL = 50 pF
(VDD = 2.7 to 3.6 V, Ta = –25 to +85°C)
Min. Typ.
Max.
Unit
—
64
—
kHz
—
128
—
kHz
40
50
—
8
40
50
60
%
—
kHz
60
%
100
—
—
ns
100
—
—
ns
100
—
—
ns
100
—
—
ns
—
—
100
ns
—
—
100
ns
—
—
100
ns
—
—
100
ns
Digital Input Timing (Normal-sync)
BCLK
SYNC
PCMI
PCMEI
0
1
2
3
4
5
6
7
8
9
10
tBS
tSB
tWS
tDS
tDH
MSB
LSB
Digital Input Timing (Short-frame-sync)
BCLK
SYNC
PCMI
PCMEI
0
1
2
3
4
5
6
7
8
9
10
tBS
tSB
tWS
tDS
tDH
MSB
LSB
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