MM74HC32 データシートの表示（PDF） - Fairchild Semiconductor

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MM74HC32

Quad 2-Input OR Gate

Fairchild Semiconductor 

Physical Dimensions (Continued)

0.43 TYP

0.65

1.65

0.45

6.10

R0.09 min

12.00°TOP & BOTTOM

A. CONFORMS TO JEDEC REGISTRATION MO-153,

VARIATION AB, REF NOTE 6

1.00

B. DIMENSIONS ARE IN MILLIMETERS

C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,

AND TIE BAR EXTRUSIONS

D. DIMENSIONING AND TOLERANCES PER ANSI

Y14.5M, 1982

E. LANDPATTERN STANDARD: SOP65P640X110-14M

F. DRAWING FILE NAME: MTC14REV6

R0.09min

Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

©1983 Fairchild Semiconductor Corporation

MM74HC32 Rev. 1.3.0

7

www.fairchildsemi.com

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