MC74HC4514 データシートの表示（PDF） - Motorola => Freescale
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MC74HC4514
Motorola => Freescale
MC74HC4514 Datasheet PDF : 9 Pages
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MC74HC4514
FUNCTION TABLE
Latch Chip
Address Inputs
Enable Select A3 A2 A1 A0
Selected
Output
(High)
H
L
L LLL
Y0
H
L
L LLH
Y1
H
L
L LHL
Y2
H
L
L LHH
Y3
H
L
L HL L
Y4
H
L
LHLH
Y5
H
L
L HHL
Y6
H
L
L HHH
Y7
H
L
HLLL
Y8
H
L
H L LH
Y9
H
L
H LHL
Y10
H
L
H LHH
Y11
H
L
HHL L
Y12
H
L
HHLH
Y13
H
L
H HH L
Y14
H
L
H HHH
Y15
All
X
H
X X X X Outputs = L
Latched
L
L
X XXX
Data
PIN DESCRIPTIONS
ADDRESS INPUTS
A0, A1, A2, A3 (Pins 2, 3, 21, 22)
Address Inputs. These inputs are decoded to produce a
high level on one of 16 outputs. The inputs are arranged
such that A3 is the most–significant bit and A0 is the least–
significant bit. The decimal equivalent of the binary input
address indicates which of the 16 data outputs, Y0 – Y15, is
selected.
OUTPUTS
Y0 – Y15 (Pins 11, 9, 10, 8, 7, 6, 5, 4, 18, 17, 20, 19, 14,
13, 16, 15)
Active–High Outputs. These outputs produce a high level
when selected (Latch Enable = H, Chip Select = L) and are at
a low level when not selected.
CONTROL INPUTS
Latch Enable (Pin 1)
Latch Enable Input. A low level on this input stores the
data on the Address data inputs in the 4–bit latch. A high
level on the Latch Enable input makes the latch transparent
and allows the outputs to follow the inputs. Note that the data
is latched only while the Latch Enable input is at a low level.
Chip Select (Pin 23)
Chip Select Input. A high on this input produces a low level
on all outputs, regardless of what appears at the address or
Latch Enable inputs. A low level on the Chip Select input
allows the selected output to produce a high level.
TIMING DIAGRAM
INPUT A
LATCH ENABLE
CHIP SELECT
OUTPUT Y
High–Speed CMOS Logic Data
5
DL129 — Rev 6
MOTOROLA
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