MC74HC4514 データシートの表示（PDF） - Motorola => Freescale
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MC74HC4514
Motorola => Freescale
MC74HC4514 Datasheet PDF : 9 Pages
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1-of-16 Decoder/Demultiplexer
with Address Latch
High–Performance Silicon–Gate CMOS
The MC74HC4514 is identical in pinout to the MC14514B metal–gate
CMOS device. The device inputs are compatible with standard CMOS
outputs, with pullup resistors; they are compatible with LSTTL outputs.
This device consists of a 4–bit storage latch with a Latch Enable and Chip
Select input. When a low signal is applied to the Latch Enable input, the
Address is stored, and decoded. When the Chip Select input is high, all
sixteen outputs are forced to a low level.
The Chip Select input is provided to facilitate the chip–select, demultiplex-
ing, and cascading functions.
The demultiplexing function is accomplished by using the Address inputs
to select the desired device output, and then by using the Chip Select as a
data input.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 268 FETs or 67 Equivalent Gates
BINARY
ADDRESS
INPUTS
A0 2
A1 3
A2 21
A3
LATCH 1
ENABLE
CHIP
SELECT
LOGIC DIAGRAM
4–BIT
STORAGE
LATCH
4–TO–16
LINE
DECODER
11 Y0
9 Y1
10 Y2
8 Y3
7 Y4
6 Y5
5 Y6
4 Y7
18 Y8
17 Y9
20 Y10
19 Y11
14 Y12
13 Y13
16 Y14
15 Y15
ACTIVE–HIGH
OUTPUTS
PIN 24 = VCC
PIN 12 = GND
MC74HC4514
24
1
24
1
N SUFFIX
PLASTIC PACKAGE
CASE 724–03
DW SUFFIX
SOIC PACKAGE
CASE 751E–04
ORDERING INFORMATION
MC74HCXXXXN Plastic
MC74HCXXXXDW SOIC
PIN ASSIGNMENT
LATCH
ENABLE 1
A0 2
A1 3
24 VCC
23
CHIP
SELECT
22 A3
Y7 4
21 A2
Y6 5
20 Y10
Y5 6
19 Y11
Y4 7
18 Y8
Y3 8
17 Y9
Y1 9
16 Y14
Y2 10
15 Y15
Y0 11
14 Y12
GND 12
13 Y13
10/95
© Motorola, Inc. 1995
1
REV 6
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